Most engineers said the controllers supported their design flows, with many noting that Denali provides synthesis scripts. One noted, however, that it took some work to port Denali's constraints into a Design Compiler synthesis flow. In physical design, most respondents reported no difficulties with layout tools from Synopsys, Avanti and Cadence. But several respondents noted that test support could be better.
Respondents said that Denali controllers met the company's gate-size estimates. They also said Denali offers good customer support. "Whenever an issue comes up (and they do, don't get me wrong) they track it down, answer to the point, resolve or explain proper usage," said one engineer.
Users di d, however, note some "surprises." One noted "issues" with command and data FIFO documentation. Another said IP is not silicon proven. A third said it was necessary to pay detailed attention to layout planning to obtain required performance.
Several respondents said Denali memory IP offered a better solution than Synopsys' DesignWare memory IP. "We selected Denali because they are the experts," said one. "Their Databahn solution allowed us to select exactly the right features." Another said the Synopsys IP was "too simplistic" in its timing model and not suitable for operation above 133 MHz.
Perhaps most impressive, only one of the 24 respondents said he probably wouldn't use the Denali solution again. That respondent added that his company has "deep memory expertise" and that he would still recommend Denali to others.
Cooley said a future ESNUG bulletin would include comments from engineers who chose to stay with Synopsys' DesignWare memory IP solutions.