TOKYO NEC and Atmos Corp. will jointly develop merged-logic embedded DRAM chips running between 400 MHz and 1 GHz. The companies hope the technology will replace SRAM in network processors, DSPs, ATM switches and routers.
The partners expect to start shipping volume quantities of their superfast logic-memory chips on the 130-nanometer process node by summer of 2002, said Hideya Horikawa, design-engineering manager of NEC Electronics Inc. They will prototype parts on the 0.13-micron process in the second half of next year and launch full production beginning in 2003, he said.
NEC is contributing its recently announced logic-process-friendly metal-insulator-metal (MIM) capacitor technology, which the companies see as crucial for developing speedy embedded DRAMs. Atmos, an eDRAM design house, is adding its DRAM compiler experience. The Pescadero, Calif.-based company will also develop macrocells and test chips.
At the VLSI Technology S ymposium in Kyoto, Japan, earlier this month, NEC disclosed it had developed a stacked eDRAM process using MIM technology for the 0.15-micron node that forms capacitors at 500° C, a good 100° below the thermal budget for logic at that line width.
Officially, NEC has confirmed the technology on 4-Mbit test chips using 0.425-micron2, stacked cells, said Shuji Kishi, project manager at NEC Corp.'s ULSI Device Development Division (Kanagawa, Japan). But in fact, the company has already scaled this to "commercial densities," Kishi said. The technology, which uses tantalum oxide as an insulator, is scalable all the way down to the 100-nm node, he added.
Developed in the early 1990s, eDRAM technology has not been widely adopted because of its significant cost, performance and yield difficulties. But the main-memory makers are battling to crash through these obstacles. For example, Toshiba Corp. recently demonstrated dramatic progress in scaling eDRAM in logic to the 100-nm node, a pro cess that runs at comparatively high voltages and low speeds of 6 to 8 nanoseconds. By comparison, Kishi said NEC's eight-metal-layer process generates fast chips but is lean on process and power requirements.
Stripping capacitors of their polysilicon adds only five mask steps for the CMOS process. MIM capacitor formation requires five fewer process steps than its metal-insulation-polysilicon brothers. Between top and bottom electrode formation, silicon capacitors require stripping hemispherical-gain formation (creating roughness), rapid thermal nitration and two high-temperature annealing and 750° C oxidation steps. MIMs require only precleaning before tantalum oxide disposition and the logic-friendly 500° C oxidation process, said Kishi.
Cost containment is therefore a reality, he argued. Logic lines eyeing MIM require only three sets of new equipment, including the single-wafer-treatment oxidation process equipment. Yields have already passed the 50 percent barrier. Kishi claimed NEC co uld hit commercial DRAM's 70 to 80 percent first-cut yields.
NEC's cells are significantly bigger than Toshiba's, Kishi admitted. Toshiba's process runs at over 100 MHz; NEC's is already running at 400 MHz in "the worst case" on the company's 0.15-micron process technology. Access speeds will drop as low as 1.33 ns at the 130-nm node. The process will develop to 600 MHz and even 1 GHz when shrunk to the 130-nm node, Kishi said.
"When you combine an MPU with a large-capacity DRAM, the total speed is really determined by how fast the logic can talk to the memory," he said. "It's a key issue. We are talking about getting the DRAM macro to talk at the same speed as the MPU. This is the issue we are addressing."
The new process will run on logic-type voltages 1.5 V for the 150-nm node, 1.2 V for the 130-nm node and about 1 V for the 100-nm node, said Kishi. Cell sizes will also scale. Those on the 130-nm node process technology will be 0.35 micron2. NEC will announce sub-0.35-micr on2 size cells at this process node at this year's International Electron Devices Meeting, he added. "These speeds have blown us away," said Al Hawtin, vice president of marketing and sales at Atmos' Kanata, Ontario, operation.
Hawtin said the speed and space savings of the proposed eDRAMs would blow SRAM out of network processors in high-speed routing applications. As companies develop 10-Gbit/second OC-192 and, eventually, 40-Gbit/s 0C-768 products, they will need memory-logic hybrids that can handle peak packet rates over 32 million packets/s, he said.
OC-192, for example, requires at least 32 Mbits of wide data bus. All the while, on-chip memory space faces incessant squeezing by increasingly complex systems-on-chip. When space and speed requirements get tough, SRAM will get lost, said Hawtin.
NEC and Atmos calculated that as die area for memory increases to about 70 percent of on-chip space, SRAM can only achieve density of about 3.7 mm2 per megabit, assuming a 100-mm 2 die. Pure-logic SRAM can get to about 2.1 mm2, according to the companies' data. NEC's process takes this to about 0.8 mm2.
"Our merged logic with NEC offers under 1 mm2 that's up to eight times better than SRAM," Hawtin said.
Designers could go to a configuration of SRAM block plus network processor plus board processor but will face huge power dissipation and access-time latencies, he said. A network processor integrating 32 Mbits of SRAM would require 118 mm2 of die area even at the 130-nm node and consume "several watts" of power, according to a joint presentation by the companies.
NEC's Horikawa argued that embedding DRAM in a network processor using the company's mixed-logic process eats about 32 mm2 at 32-Mbit density at today's 150-nm design rule. Peak consumption tops out at about 500 mW. Also, embedding the memory allows for internal buses up to 1,024 bits, he said. The companies estimate the total available m arket rising from $43 million this year to $174 million as soon as 2004. Horikawa said NEC will use its marketing muscle in the United States and target fabless silicon makers as well as all the relevant network processor and DSP makers.
"If you take a DSP with voice-over-Internet Protocol, you can fit in about 10 channels per packet. If you use our eDRAM you can get about 100 channels/packet," Horikawa said. "That's an added value of about one order [of magnitude] better."
Horikawa said NEC in Japan will launch production at the company's 8-inch Kyushu fab with a maximum capacity of 10,000 wafers per month. Target applications will also include wireless codecs and voice-recognition functions.