GNSS (GPS, Galileo, GLONASS, Beidou3, QZSS, SBAS) Ultra-low power RF Receiver IP
Palmchip Receives Key System-on-Chip Patent
SAN JOSE, California, August 04, 2003 – Palmchip Corporation, a pioneer in semiconductor IP and system-on-chip technology, today announced that the US Patent and Trademark Office (www.uspto.gov) has awarded the company a key patent for the company’s technology facilitating the easy connection of IP blocks within a system on chip design. The patent (US Pat. No. 6,601,126), titled Chip-core Framework for Systems-On- a-Chip, will protect the company’s technology for building system on chips using a unidirectional bus structure enabling point-to-point connectivity for internal SoC IP cores. This technology was initially introduced to the chip design community through the company’s CoreFrame® SoC architecture.
The CoreFrame SoC architecture is used in Palmchip’s two SoC platform products, PalmPak™ and the flagship AcurX™ platform. Both platforms are configurable and are tested, pre-verified and silicon proven.
"This favorable decision from the U.S. Patent and Trademark Office represents a significant milestone in our company's history," said Jauher Zaidi, President and CEO of Palmchip Corporation. "The granting of this patent validates our SoC technology leadership and reflects our history of innovation in system on chip platform design in addition to protecting our intellectual property."
"We believe that this patent grant could have a wide-ranging impact on those companies who have created SoC devices or marketed SoC platforms using unidirectional busses as a method of assembling separate IP blocks within a design," said Jim Venable, vice president of Palmchip. "It is our intention to aggressively protect our intellectual property by making the technology available under license to those companies wishing to use it."
About Palmchip Palmchip
Corporation develops and licenses configurable SoC platforms, subsystems, and IP cores for embedded SoC's used in a variety of applications. Palmchip's IP is based on its CoreFrame® integration technology. This technology is independent of processor, I/O or foundry, allowing designers flexibility in porting IP from any number of sources. Palmchip was established in 1996 and is today a privately held company based in San Jose, California (USA). More information can be obtained at www.palmchip.com.
Palmchip, the palm leaf logo and CoreFrame are registered trademarks of Palmchip Corporation. AcurX, PalmPak, Matrix, Timing Taps, and CrosSwitch are trademark of Palmchip Corporation. All other trademarks are the property of their respective owners
|
Related News
- DAFCA Receives $1.8 Million ATP Grant to Develop Reconfigurable Infrastructure Platform for System-on-Chip Electronics
- Palmchip Introduces New AcurX Series of Configurable System-On-Chip Platforms for Mega-gate Chip Designs
- Palmchip Introduces New GreenLite™ II Family of Complete System-On-Chip IP Solutions for Disk Drive Control <!--<FONT SIZE=-1>(by Peter Clarke - EE-TIMES)</FONT>-->
- Palmchip to Include inSilicon Intellectual Property in System-on-Chip Platforms
- Saankhya Labs receives approval under Semiconductor Design Linked Incentive (DLI) scheme for Development of a System-on-Chip (SoC) for 5G Telecom infrastructure equipment
Breaking News
- Ultra Accelerator Link Consortium (UALink) Welcomes Alibaba, Apple and Synopsys to Board of Directors
- Breaking Ground in Post-Quantum Cryptography Real World Implementation Security Research
- RIKEN adopts Siemens' emulation and High-Level Synthesis platforms for next-generation AI device research
- CAST to Enter the Post-Quantum Cryptography Era with New KiviPQC-KEM IP Core
- InPsytech Announces Finalization of UCIe IP Design, Driving Breakthroughs in High-Speed Transmission Technology
Most Popular
- Eighteen New Semiconductor Fabs to Start Construction in 2025, SEMI Reports
- InPsytech Announces Finalization of UCIe IP Design, Driving Breakthroughs in High-Speed Transmission Technology
- Imagination pulls out of RISC-V CPUs
- Chip Interfaces Successfully Completes Interlaken IP Interoperability Test with Cadence 112G Long-Reach PHY
- RISC-V in AI and HPC Part 2: Per Aspera Ad Astra?
E-mail This Article | Printer-Friendly Page |