Structured-ASIC debate building in fervor
08/22/2003 4:00 PM EST
A custom-chip design approach that has come to be known as "structured ASIC" was initially dismissed by critics as a fad, but it is proving to have staying power as system architects increasingly seek a middle ground between cell-based designs and FPGAs.
Suppliers say they are racking up orders for structured ASICs across all application segments, with the bulk of activity in communications infrastructure and storage, where unit volumes would justify the expense of a cell-based design.
In-Stat/MDR, Scottsdale, Ariz., forecasts a rapid uptake for the technology, with revenue reaching $460 million by 2007--possibly higher if the economy improves in the next few years, said analyst Jerry Worchel.
And EBN has learned that a formal industry association is taking shape with the aim of bringing credibility to the concept. Sources said the first step would be establishing an accepted definition of structured ASIC, which takes many forms but generally consists of embedded design blocks surrounded by customizable logic gates. Though details of the group are being closely guarded for now, participants are said to include 90% of existing structured-ASIC suppliers, as well as EDA companies.
One key player has chosen to sit it out for now. LSI Logic Corp. said it declined an invitation to participate in the structured-ASIC association, believing its "platform" approach to be in a different weight class.
By any name, the idea of cutting development time by starting with a partially configured device that has ASIC-like performance and doesn't cost an arm and a leg, relative to FPGAs, has begun to resonate with customers.
"The proposition is really good--it's one-tenth of the NRE, so instead of $1 million you spend only $100,000. All the solutions out there are pretty much the same in this respect," said Mobashar Yazdani, manager of ASIC and ASSP technology in the Electronic Systems Technology Center at Hewlett-Packard Co., Palo Alto, Calif. "But it's not as simple as it looks.
"The main thing we are concerned with is will it fit with what we do: what kind of IP goes in, how do they arrange the IP, and how do you model this thing [for verification]," Yazdani said. "Then we look at whether the per-unit part price is good--it's generally almost twice what an ASIC would be [but less than an FPGA]. Where it seems to make the most sense is about 10,000 to 100,000-unit volumes."
Suppliers contend the potential cost saving is powerful enough on its own.
"We're finding that because time-to-market and low cost of entry are such strong forces, customers are making compromises to make their designs fit to the platform," said Mark Nelson, RapidChip marketing director at LSI Logic, Milpitas, Calif.
The tradeoffs might be simply choosing to repartition a 12 million-gate design into two or three structured ASICs, or giving up a little performance at the chip level and tweaking the system architecture to compensate.
LSI Logic is one of several vendors that have pitched a platform-ASIC approach to Hewlet-Packard, according to Yazdani, who has also heard from AMI, Chip Express, Lightspeed, NEC, and Leopard Logic, a reconfigurable-IP developer that recently recast itself as a chip company.
Hewlett-Packard is "experimenting" with a slice from one of these, though Yazdani declined to say which one.
"The jury's still out," he said. "Until you route, you don't know whether everything will fit and work at speed."
LSI Logic claims to have at least one design contract in each of eight different applications with customers in Europe and North America, using RapidChip slices in 0.18- and 0.11-micron technology.
"We're getting design wins both with existing cell-based ASIC customers and with customers we haven't or wouldn't have dealt with in the cell-based arena before," Nelson said.
Meanwhile, NEC Electronics Inc. has made deep inroads with 26 purchase orders logged for its Instant Silicon Solution Platform (ISSP), many of those having bumped out FPGAs, said Chung Ho, director of custom LSI product development at NEC, Santa Clara, Calif.
"Some customers would not have even considered going into a fixed solution if ISSP had not been available," Ho said.
FPGA suppliers are feeling the heat. Altera Corp., which claims to have pioneered the structured-ASIC approach with its HardCopy FPGA-to-ASIC conversion technology, recently stepped up its attack on traditional ASIC business by offering a way to design HardCopy ASICs without an FPGA.
"The big difference we have is that the underlying technology is orders-of-magnitude less expensive, and the tools are much more accessible," said Tim Colleran, vice president of product marketing for Altera in San Jose.
FPGA rival Xilinx Inc. has been among the harshest critics of structured ASICs, saying that they bring to bear all the negatives of traditional gate arrays and a whole lot of new challenges.
Besides having to select the right IP and the right placement of the IP to cover a diverse set of designs, structured-ASIC vendors face alienating their EDA software partners by forcing down tool prices, said Babak Hedayati, senior director of business development at Xilinx, San Jose.
"To compete, they have to have fully loaded, fully integrated software environments at a very low cost," Hedayati said. "In trying to reduce what is normally a $150 million license to $10 million, they're pissing off their ecosystem."
Nevertheless, gate array suppliers reported renewed interest from customers since updating their products to use IP and state-of-the-art process technology. Chip Express Corp.'s book-to-bill ratio was 1.2 in the most recent quarter, mostly for applications that involve FIR filters and multiply-and-accumulate blocks, said Doug Bailey, vice president of marketing at the Santa Clara-based company.
Bailey said 90% of the structured ASIC designs Chip Express takes are prototyped in an FPGA to save development cost, but for reasons of performance were always targeted for production in an ASIC.
AMI Semiconductor Inc. sees a similar pattern in its business, said Vince Hopkin, vice president of digital ASICs at the Pocatello, Idaho, company. "The IP we embed and a lot of the methodology is targeting FPGA conversions, so customers can do drop-in replacements," Hopkin said.
Hence the criticism. Yet there is enough difference between structured-ASIC offerings to satisfy the needs of system designers for a long time to come, In-Stat/MDR's Worchel said.
"You could argue structured ASIC is a glorified gate array, but still there's the void [between ASICs and FPGAs]," he said. "How many high-end FPGAs can you really afford to use at $1,500 to $2,000 a pop?"
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