SAN JOSE, Calif. – August 25, 2003 – Today 0-In Design Automation, the Assertion-Based Verification Company, announced that it has been granted U.S. Patent Number 6,609,229, entitled “Method for automatically generating checkers for finding functional defects in a description of a circuit” which covers methods of specifying and generating assertions for use in simulation.
“0-In pioneered assertion-based verification,” explained Dr. Curtis Widdoes, 0-In’s Chairman and Chief Technical Officer. “Very early on, our customers told us that it was critical to make assertions easy to use. With their guidance, we developed a wide range of methods and technologies for design engineers and verification engineers to easily specify and use assertions. The newly granted patent covers those methods and technologies.”
0-In is committed to making the power of assertion-based and formal verification technologies available to every chip designer and every verification engineer. “We believe that advanced verification technologies are successful only when they are easy enough to use that they can be adopted without the help of specialists,” said Dr. Widdoes. “Our goal is to make specification of assertions effortless, so that every member of the development team can put assertions into the design.” As part of this effort, 0-In is a strong proponent of standards and interoperability and is an active member of Accellera. The 0-In Assertion-Based Verification suite of tools and CheckerWare® verification IP library support Accellera and IEEE standards.
Products currently being shipped by 0-In incorporate the methods and technologies covered by the newly granted patent.
0-In Design Automation, Inc. (pronounced "zero-in") develops and supports functional verification products that help verify multi-million gate application-specific integrated circuit (ASIC) and system-on-chip (SoC) designs. The company delivers a comprehensive assertion-based verification (ABV) solution that provides value throughout the design and verification cycle – from the block level to the chip and system level. Twelve of the 15 largest electronics companies have adopted 0-In tools and methodologies in their integrated circuit (IC) design verification flows. 0-In was founded in 1996 and is based in San Jose, Calif. For more information, see http://www.0-in.com.
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