Synopsys and Denali Link Verification Products to Enable Testbench Reactivity for Memory Transactions
MOUNTAIN VIEW, Calif.--(BUSINESS WIRE)--June 18, 2001--Synopsys, Inc. (Nasdaq:SNPS) and Denali Software, Inc., today announced an integrated solution that gives a VERA testbench real-time access to system data from memory components. This integration of Synopsys' VERA(TM) testbench automation tool coupled with the OpenVera(TM) hardware verification language and Denali's Memory Modeler Advanced Verification (MMAV) product gives users the ability to leverage memory data and memory transaction for advanced system verification.
The traditional approach for creating testbenches treats memory components as black boxes, which shows only the data on the buses going to and from the memory. However, by integrating with VERA, Denali provides VERA testbenches with direct access to the internals of the memory devices. In addition, Denali's MMAV enables easy access to high-level data structures that may be stored across multiple memory devices. Now, VERA users can use memory data and transactions at the both device level and at a high-level to dramatically enhance the verification process.
Using rules or assertions on memory transactions, the interactive OpenVera testbench can react to specific kinds of data or actions on the contents in memory. For example, the designer can set a call back to the VERA testbench whenever a memory transaction is written to an illegal address or if the transaction contains particular values. The callbacks can also be used to catch bugs associated with memory transactions, such as consecutive reads or writes to the same address. This data-driven approach provides a new source of data for VERA testbenches and helps designers debug using real design data. The interface is transparent to VERA users, and does not require them to learn additional tools to make use of the data-driven verification.
Communications designers have shown early interest in the joint solution. AcceLight Networks (Ottawa, Canada and Pittsburgh, PA), a beta site for the integrated solution, used the VERA testbench automation tool and MMAV combination to perform high-level verification on their Photonic Service Switch product.
``Together, Synopsys' VERA and Denali's MMAV enable us to validate that the entire system is operating correctly,'' said Dr. Paul Chow, director of ASIC Technology and co-founder at AcceLight Networks. ``High-level verification ensures the reliability we need in our fast-switching technology. The ability to perform high-level verification early in the design cycle means we can get our products to the market faster.''
``The integration of Synopsys' VERA testbench automation tool coupled with the OpenVera hardware verification language and Denali's MMAV provides testbenches with real-time access to system data from memory components. This integration reduces overall verification time for our customers' most challenging verification problems,'' said Kevin Silver, vice president of marketing at Denali Software, Inc.
``Our high performance VCS Verilog simulator and Scirocco VHDL simulator already work with MMAV; we are pleased to see this integration is now extended to the VERA testbench tool,'' said Farhad Hayat, vice president of marketing, verification technology group at Synopsys. ``The growing number of tools supporting OpenVera benefits end users by simplifying and accelerating the creation of complete, interoperable verification environments. The Vera Open Source Initiative is enabling our customers to have access to a broad set of verification tools based on an open language.''
Complete Functional Verification Solution
Synopsys provides a complete line of functional verification solutions supporting Verilog, VHDL, mixed-HDL, and mixed-signal complex SoC designs aimed at achieving the highest functional coverage in the shortest amount of time. These solutions include Synopsys' VCS(TM) Verilog simulator, Scirocco(TM) VHDL simulator, VCS/Scirocco-MX mixed-HDL simulation, VERA(TM) testbench automation tool, CoverMeter(TM) Verilog code coverage analysis tool, DesignWare® verification IP, LEDA® programmable HDL checker, NanoSim(TM) circuit simulation, and Formality® equivalence checker.
Synopsys, Inc. (Nasdaq:SNPS), headquartered in Mountain View, California, creates leading electronic design automation (EDA) tools for the global electronics market. The company delivers advanced design technologies and solutions to developers of complex integrated circuits, electronic systems, and systems on a chip. Synopsys also provides consulting and support services to simplify the overall IC design process and accelerate time to market for its customers. Visit Synopsys at http://www.synopsys.com.
About Denali Software, Inc.
Denali Software, Inc. is the world's largest provider of comprehensive solutions for memory subsystem modeling, simulation and verification. Denali delivers its extensive database of memory models, powerful design verification software, and memory processor IP through its dedicated platform, eMemory.com. More than 3000 designers worldwide use Denali's tools, technology, and services to efficiently integrate new memory technologies into complex system designs for communication, consumer, and computer products. For more information, contact Denali at http://www.denalisoft.com or call 650/325-7241.
Note to Editors: Synopsys, Formality, DesignWare, LEDA and VERA are registered trademarks of Synopsys, Inc. VCS, Scirocco, CoverMeter, and NanoSim are all trademarks of Synopsys, Inc. All other trademarks or registered trademarks mentioned in this release are the intellectual property of their respective owners.
Contact: Synopsys, Inc.
Catherine Glines-Dickson, 650/584-4170
Denali Software, Inc.
Kevin Silver, 512/454-7004 ext. 230
KVO Public Relations
Amy Garland, 503/221-2387