Complete High-Speed USB 2.0 PHY IP Provides Mixed-Signal Physical Layer for Next Generation Processes
MOUNTAIN VIEW, Calif., August 26, 2003 - Synopsys, Inc. (Nasdaq:SNPS), the world leader in semiconductor design software, today announced that it has received the industry's first Universal Serial Bus (USB) Implementers' Forum certification for its DesignWare® Cores USB 2.0 PHY (physical layer) intellectual property (IP). The certified core supports all USB 2.0 speeds: high speed, full speed and low speed, and is compliant with the USB 2.0 Transceiver Macrocell Interface (UTMI+) specification. The certification means that system-on-chip (SoC) designers can implement fast USB interfaces in deep submicron geometries.
"We use the USB interface in many applications, including high volume, consumer product ASICs," said Keith Windmiller, ASIC Product Division R&D manager at Agilent Technologies. "Our comprehensive IP portfolio, which includes Synopsys' certified USB PHY core, is a key enabler in the rapid integration of first-time-right silicon."
Synopsys' DesignWare USB 2.0 PHY is a complete solution, designed for single-chip USB 2.0 integration in both device and host applications. The USB 2.0 PHY includes all the required logical, geometric and physical design files to implement USB 2.0 capability in an SoC design and fabricate the design in the designated foundry. With this announcement, the foundry process for the USB 2 PHY extends to a 0.13-micron CMOS digital logic process. The 40X acceleration in data rate offered by USB 2.0 improves the performance of many applications, including desktop systems, video cameras, portable storage, external CD-R/W, optical scanners, inkjet and laser printers, TV tuners and audio speakers.
"The ongoing efforts of Synopsys to make its certified core available across a range of process technologies will help accelerate the development and deployment of USB 2.0 SoC designs," said Jeff Ravencraft, chairman and president, USB Implementers Forum. "This certification means that design engineers who want to take advantage of the increased performance of the USB 2.0 standard will have a silicon-proven solution from a technology and market leader."
"This latest certified release of the DesignWare USB 2.0 PHY core demonstrates Synopsys' continued leadership in providing USB IP and helps reduce the IP implementation risk for our customers," said Kevin Walsh, director of marketing for DesignWare Cores at Synopsys. "Engineers who want to take advantage of the higher performance of the USB 2.0 specification can now apply it to the most advanced silicon processes for their complex SoC designs."
Synopsys, Inc. (Nasdaq:SNPS) is the world leader in electronic design automation (EDA) software for semiconductor design. The Company delivers technology-leading semiconductor design and verification platforms to the global electronics market, enabling the development of complex systems-on-chips (SoCs). Synopsys also provides intellectual property and design services to simplify the design process and accelerate time-to-market for its customers. Synopsys is headquartered in Mountain View, California and has offices in more than 60 locations throughout North America, Europe, Japan and Asia. Visit Synopsys online at http://www.synopsys.com/.
Synopsys and DesignWare are registered trademarks of Synopsys, Inc. All other trademarks or registered trademarks mentioned in this release are the intellectual property of their respective owners.