KYOTO, Japan Toshiba Corp. came to Kyoto, Japan's VLSI Technology Symposium with a 100-nanometer (0.10-micron) system-on-chip (SoC) technology that supports embedded DRAM and mixed-signal capabilities.
Katsura Miyashita, an engineering manager at the Toshiba system LSI division (Yokohama, Japan), said that while many companies have developed high-performance, sub-100-nm gate CMOS technologies, Toshiba is the first to announce that it has integrated logic, SRAM and analog devices with high-speed embedded DRAM (eDRAM) and embedded SRAM at the 100-nm node.
The 100-nm SoC platform has three types of MOS field-effect transistors (MOSFETs). Toshiba created a 1-volt high-performance version aimed at microprocessors for engineering workstations. The company is aiming a second high-performance type running at 1.2 volts at notebooks, network applications and graphics chips. The company's third, a low-leakage type, operates at 1.2 volts and is int ended for mobile phones and PDAs. Toshiba has also optimized 1.8-V MOSFETs for high-speed I/O and mixed-signal applications. The LSI uses 2.5-V and 3.3-V MOSFETs for the eDRAM.
"Many customers want one chip, especially for cell phones, graphics and network applications," said Fumitomo Matsuoka, senior specialist at Toshiba's system LSI division.
"The basic concept is to adopt a versatile core logic, eDRAM and analog I/O device suitable for use as high-performance microprocessors in notebook PCs and mobile phones," he said.
The logic process is compatible with Toshiba's 0.18-micron2 trench capacitor DRAMs. The company claimed its 1.25-micron2, six-transistor SRAM cells are the smallest reported for embedded memory cells.
Toshiba used 193-nm argon-fluoride lithography for several critical layers. The device takes advantage of a triple-gate oxide process and the company has fitted metal-insulator-metal capacitors using tantalum oxide. The SoC uses 11 copper layers and low- k dielectrics.
Direct tunneling between the gate and substrate in oxide films has become one of the biggest issues for engineers making gate oxides for the 100-nm technology node. Engineers have juggled with lightly nitrided silicon dioxide compounds as part of the search for silicon dioxide alternatives. The International Technology Roadmap for Semiconductors announced that the tunneling problem is a major stumbling block for developing SoCs at that technology node.
"Down to 0.13 micron, subthreshold leakage is the main sticking point," said Miyashita.
"But at the 0.10-micron level, if we use very thin oxides, less than 2-nm thick, tunneling current becomes an issue. We needed a thinner gate oxide," he said.
Toshiba engineers optimized the nitrogen in their silicon oxynitride gate oxide to produce a gate oxide material that allowed about 10 times lower direct tunneling gate current than that of silicon dioxide, said Miyashita. The company is exploring using high-k dielectrics for 0.07- an d 0.05-micron process technology SoCs, he said.
SoC designers have also run into major obstacles when embedding high-speed eDRAM in logic. The company's trench capacitor DRAM process works to clear those obstacles much better than rivals' planar capacitor eDRAM process, the company claims.
"In a stack process, a thermal budget is required and this impacts the MESFETs' performance," said Hidemi Ishiuchi, group manager of Toshiba's advanced CMOS technology development group.
"But we have the trench already formed. The MESFET process is mainly the same as the logic process. It's really good for integration," he said.
Matsuoka said the company decided to push eDRAM integration because engineers now believe eDRAM SoC technology will become one of the "driving forces" of Toshiba's semiconductor business. Matsuoka said Toshiba will sample both eDRAM SoCs and the company's conventional CMOS-based devices at the 0.10 -micron technology node in the third quarter of 2002.
"This is the world's fir st logic embedded SoC at 0.10 micron. From our integration strategy viewpoint, eDRAM is the technology of the future. I think all the other companies plan to release eDRAM after their pure CMOS, but we plan to do it simultaneously," he said.
While the SoC's eDRAM cannot match pure DRAM's retention, Matsuoka said he believed the 100-nm eDRAM design platform would be competitive with stand-alone SDRAM and DRAM.
Embedded DRAM cell sizes will always be about 10 to 15 percent larger than conventional DRAM cells because of the embedded DRAM integration process. On the macro side, this overhead reduces to just a few percent, he argued. Next year's production parts will have read-write times of 6 to 8 nanoseconds. Toshiba will produce the SoCs at 32- and 64-Mbit densities, and plans to take the parts up to 256-Mbit densities.
Matsuoka said Toshiba's SoC road map requires the company to push for each new technology node every 18 months. The company is shrinking design rules 83 percent each 12 months and aims to boost performance for example by cutting delay times 30 percent each generation. This road map will be followed until the 0.07-micron process node, he said.
Matsuoka also said the company is considering developing high-performance versions of the SoC on silicon-on-insulator technology.
"We are just developing this technology, and we are aiming to start releasing products on SOI from the CMOS IV [0.10-micron node] generation," he said.