Synopsys' VERA Adopted by Transmeta for Verification of Crusoe Family of Microprocessors
MOUNTAIN VIEW, Calif.--(BUSINESS WIRE)--June 13, 2001--Synopsys, Inc. (Nasdaq:SNPS), the technology leader for complex IC design, today announced that Transmeta Corporation has adopted its VERA® testbench automation tool and is widely adopting the OpenVera(TM) Hardware Verification Language to meet their challenging verification needs. Using the VERA testbench tool and OpenVera language, Transmeta was able to meet their stringent verification requirements and quickly bring to market the energy-efficient Crusoe microprocessor. After successful use of VERA on the first generation Crusoe processors, Transmeta is expanding its usage of VERA for the success of future Crusoe designs.
``To design a processor that simultaneously offers long battery life, high performance and x86 compatibility is a challenging undertaking requiring a structured approach to verification. By using VERA we were able to meet our stringent quality targets and greatly improve verification productivity,'' said Godfrey D'Souza, director of VLSI Development, Transmeta Corporation. ``Our verification team has found the OpenVera language easy to learn, which helped them to come up to speed quickly and be productive. We look forward to leveraging the OpenVera language and tools in the future to develop our next generation energy-efficient Crusoe microprocessors.''
Functional verification of microprocessors is highly resource intensive and requires the generation of many different assembly programs and bus transactions to exercise different aspects of the design. VERA addresses this need with a unique stream generation capability that automatically generates rules-driven bus transactions and assembly programs. This capability delivers significant productivity for verification of processor designs by generating random combinations of legal bus transactions and instruction sequences to verify corner cases in the design.
``We are pleased that Transmeta is expanding its usage of OpenVera and the VERA testbench tool for the verification of the Crusoe line of microprocessors,'' said Farhad Hayat, vice president of marketing of the Verification Technology Group at Synopsys. ``VERA is specially designed for verification of complex designs requiring rules-driven stimulus generation, and for this reason, it is deployed at many leading semiconductor, networking, and systems companies.''
Complete Functional Verification Solution
Synopsys provides a complete line of functional verification solutions supporting Verilog, VHDL, mixed-HDL, and mixed-signal complex SoC designs, aimed at achieving the highest functional coverage in the shortest amount of time. These solutions include Synopsys' VCS(TM) Verilog simulator, Scirocco(TM) VHDL simulator, VCS/Scirocco-MX mixed-HDL simulation, VERA® testbench automation tool, CoverMeter(TM) Verilog code coverage analysis tool, DesignWare® verification IP, LEDA® programmable HDL checker, NanoSim(TM) circuit simulation, and Formality® equivalence checker.
Synopsys, Inc. (Nasdaq:SNPS), headquartered in Mountain View, California, creates leading electronic design automation (EDA) tools for the global electronics market. The company provides comprehensive design technologies and solutions to developers of complex integrated circuits, electronics systems, and systems on a chip. Synopsys also provides consulting and support services to simplify the overall IC design process and accelerate time to market for its customers. Visit Synopsys at http://www.synopsys.com.
Note to Editors: Synopsys, Formality, DesignWare, LEDA and VERA are registered trademarks of Synopsys, Inc. VCS, Scirocco, CoverMeter, and NanoSim are all trademarks of Synopsys, Inc. All other trademarks or registered trademarks mentioned in this release are the intellectual property of their respective owners.
Synopsys, Inc., Mountain View Renae Cunningham, 650/584-1902 firstname.lastname@example.org or KVO Public Relations Amy Garland, 503/221-2387 email@example.com