SAN MATEO, Calif. In an indication of the growing importance of reusable intellectual property to fabless chip makers, the Fabless Semiconductor Association (FSA) and the Virtual Socket Initiative Alliance (VSIA) will jointly announce on Monday (Sept. 22) that they have agreed to pool resources on developing and rolling out a quality metric for IP cores.
The work will be performed within the VSIA's Development Working Group (DWG) structure. VSIA has had a Quality DWG at work for some time. In August, the group formally announced a metric and procedures for quantifying the quality of a piece of IP.
The metric is based on a checklist of deliverables and attributes. The checklist is used, then multiplied by a list of weights, expressing the degree of importance a design team attaches to each attribute. Finally, a figure of merit is derived.
VSIA's initial work was intended specifically for soft IP. The agreement will bring FSA's resource s into play to work with the VSIA DWG in extending the metric to hard IP.
Vin Ratford, chairman of the FSA's IP Education Working Group, will chair a sub-group within the VSIA DWG to bring this about. Ratford hopes to conclude the effort and announce a metric for hard IP evaluation within a year.
The two organizations will also cooperate on what the VSIA calls an Adoption Group, that is , a team that will focus on the challenges to getting the new metrics supported by industry tools, adopted and into common use in the design community.
The efforts represent the first formal cooperation between the two organizations, which have increasingly found themselves trying to help the same member companies with similar challenges like IP reuse as it becomes a mainstream technique for not only ASIC but also merchant IC design.