Kaben Licenses Programmable Clock Generator in TSMC 0.18um Digital CMOS
"Versatile Clock to Generate Output Frequencies from 1 and 120MHz in 1kHz steps."
Ottawa, ON - September 22, 2003 - Kaben Research Inc., a developer of mixed-signal, intellectual property (IP) blocks for wireless manufacturers, announced today that they have licensed to a lead customer a Programmable Clock Generator in TSMC 0.18mm pure digital CMOS.
The Kaben KR-PCG-120-TS18 Clock Generator accepts a crystal frequency input from 10 to 50MHz and generates a low jitter output between 1 and 120MHz in steps of less than 1kHz. The output frequency range is from 12 times to 1/64th of the crystal reference frequency. The cell can be used to clock Microprocessors, DSPs, Digital Logic, A/Ds, and D/As. The product is designed in a process that has only digital CMOS available which allows the IP cell to be dropped into low cost designs.
"Kaben's Clock Generator IP block enables SoC manufacturers to use a single low-power design across most of their products." said Seste Dell'Aera, Kaben's VP Marketing. "The fine resolution and wide frequency range offer a tremendous flexibility to the system designer."
About Kaben
Kaben Research is an IP company focused on design, development, and licensing of mixed-signal building blocks that are key to creating future SoC products. The company delivers high-performance, proven IP blocks to SoC manufacturers in the wireless communications market that significantly reduce risk, cost, and time to market. For more information, please visit www.kabenresearch.com.
|
Related News
- Kaben Research Developing a Delta-Sigma Modulator in TSMC 0.18um CMOS
- Atmel Announces 0.18um RF CMOS Foundry Process for Low Volume Applications
- SMIC Adds New Design Kit for its 0.18um CMOS Process for Use with Agilent Technologies'EDA Software
- ChipIdea's 210MHz Analog Interface for Flat Panel Displays Validated in Silicon at 0.18um TSMC
- Chipidea announces silicon validated analog IP cores in Chartered 0.18um CMOS Process
Breaking News
- Arteris Joins Intel Foundry Accelerator Ecosystem Alliance Program to Support Advanced Semiconductor Designs
- SkyeChip Joins Intel Foundry Accelerator IP Alliance
- Siemens and Intel Foundry advance their collaboration to enable cutting-edge integrated circuits and advanced packaging solutions for 2D and 3D IC
- Cadence Expands Design IP Portfolio Optimized for Intel 18A and Intel 18A-P Technologies, Advancing AI, HPC and Mobility Applications
- Synopsys and Intel Foundry Propel Angstrom-Scale Chip Designs on Intel 18A and Intel 18A-P Technologies
Most Popular
- QuickLogic Delivers eFPGA Hard IP for Intel 18A Based Test Chip
- Siemens collaborates with TSMC to drive further innovation in semiconductor design and integration
- Aion Silicon Joins Intel Foundry Accelerator Design Services Alliance to Deliver Next-Generation Custom SoCs at Scale
- TSMC Unveils Next-Generation A14 Process at North America Technology Symposium
- BOS Semiconductors to Partner with Intel to Accelerate Automotive AI Innovation
![]() |
E-mail This Article | ![]() |
![]() |
Printer-Friendly Page |