Motorola Discloses Next Generation PowerPC System on Chip Solution The e500 PowerPC Book E-compliant Core Enables Intelligent Services At Faster Speeds for Network Infrastructure, Automotive, And Embedded Control Applications
SAN JOSE, Calif., Jun 12, 2001 /PRNewswire/ -- Motorola (NYSE: MOT), the leading supplier for high-performance networking and automotive embedded processors, disclosed details of its new e500 PowerPC(TM) Book E core today at the MicroDesign Resources' Embedded Processor Forum. Designed to be highly configurable to meet the specific needs of the embedded market, the e500 core, based on the PowerPC Book E architecture, provides next generation system on chip (SoC) solutions while balancing performance, area and power.
For higher general performance, the e500 core targets a clock rate of 800MHz in Motorola's HiPerMOS7 (HiP7) 0.13 um CMOS (complementary metal oxide semiconductor) processor platform technology, while keeping the core area to a mere 6 square millimeters and power down at 3mW/MHz.
"Motorola's e500 core will provide customers with a superior CPU system core for SoCs used in today's networking and embedded applications," stated Cary D. Snyder, senior analyst, Microprocessor Report. "I believe that products using the e500 core will do very well in the network and communication application areas that have put Motorola in its preeminent position in these markets."
Delivering flexibility for application-specific optimizations, the e500 core leverages application processing units (APUs) for instruction set extensions that are provided for by the PowerPC Book E architecture. The integer select (isel) extension is engineered to provide simple predicated moves to remove branches, reduce code footprint and improve determinism.
The context management APU is designed to enable a shadow register set to accelerate context save and restore and to provide extremely fast context switching. A third APU was developed to provide very substantial DSP performance while using very little silicon. Additionally, the e500 core delivers cache control capabilities by providing cache-line locking by software for all cache structures, including the branch prediction cache. The e500 core is expected to provide 1800 Dhrystone 2.1 MIPS processing power at 800 MHz. With the Signal Processing APU deployed, a peak level of 1600 MMACs (millions of multiply-accumulates per second) is available, while 256-point FFTs may be completed in a little over 5000 clock cycles -- in single length floating point. With a core voltage at 1.5V, the core's typical power dissipation is projected to be 3 mW/MHz at 800 MHz. Motorola's PowerPC cores are designed to control power by varying frequency while providing automatic dynamic power-down of idle function units.
Technical Feature Summary:
- 32-bit Book E extensions, PowerPC architecture
- 2-way superscalar, 7-stage pipeline design, 800MHz at 105 degrees C
- Scalable caches 0-32KB for both I- and D-
- Two-level software-managed Book E MMU providing support for page sizes from 4KB to 256MB
- 512 entry Branch Target Buffer
- Cache line lockability for I-cache, D-cache and BTB
- Optional APUs include:
- Integer select extension for branch optimization
- Signal processing supported by 2-way SIMD unit with integer, fractional, saturated, unsaturated and floating point operations, together with a MAC unit wth dedicated accumulator
- Low latency, low overhead context switching for tasks and interrupts
- Rich, high-performance interface specification providing nearly 20GB/sec of raw on-chip bandwidth
The e500 core will initially be offered for industrial temperature applications (105 degrees C junction, 800MHz) and automotive applications (150 degrees C junction at 200MHz) with products expected to be available in the first half of 2002. Motorola also expects future products based on the e500 core to be capable of lower-voltage operation to further reduce power dissipation.
As the world's #1 producer of embedded processors, Motorola's Semiconductor Products Sector offers multiple DigitalDNA(TM) technologies which enable its customers to create "smart" products and new business opportunities in the networking and computing, wireless communications, transportation, and home networking markets. Motorola's worldwide semiconductor sales were $7.9 billion (USD) in 2000. http://www.motorola.com/semiconductors/
Motorola, Inc. (NYSE: MOT) is a global leader in providing integrated communications and embedded electronic solutions. Sales in 2000 were $37.6 billion. http://www.motorola.com
MOTOROLA, the Stylized M Logo and all other trademarks indicated as such herein are trademarks of Motorola, Inc. (R) Reg. U.S. Pat. & Tm. Off. PowerPC is a trademark of International Business Machines Corporation and used by Motorola, Inc. under license.
For further information, please contact: Andrea Crocker of Motorola, 512-996-6387, email@example.com; or Jennifer Richter of MS&L Global Technology, 805-230-8280, firstname.lastname@example.org, for Motorola.
Andrea Crocker of Motorola, 512-996-6387,
email@example.com; or Jennifer Richter of MS&L Global Technology,
805-230-8280, firstname.lastname@example.org, for Motorola