SAN JOSE, Calif. The HyperTransport Consortium has unveiled optional upgrades to its protocol specification to open the door to greater use of its interconnect for handling data plane packet traffic in communications systems. The 1.1 version of HyperTransport, called DirectPacket, includes four changes the group expects to see some members support in silicon in the next six to 18 months.
The announcement comes just two weeks after the rival RapidIO consortium announced flow-control mechanisms aimed at making its interconnect more useful in handling data plane packet traffic in telecom gear. RapidIO is closely tied to PowerPC processors from Motorola and IBM while HyperTransport is linked to Advanced Micro Devices X86 processors and MIPS-based communications chips from Broadcom, PMC-Sierra and others.
The key aspect of the HyperTransport upgrade is a native packet handl ing mechanism that brings message passing semantics to what has been the memory-mapped load/store architecture. The feature is implemented by reusing low-level address bits, thus avoiding any additional protocol overhead for packet handling.
In tandem, DirectPacket offers a peer-to-peer routing capability to let nodes in a comms system communicate directly without going through a host processor. The feature was required to overcome the PCI compatibility built into HyperTransport that defines a PCI-like master/slave relationship between systems devices, something not desirable in most multihost communications systems.
Capping off the packet-processing features, DirectPacket includes three new sets of virtual channels aimed to simplify bridging HyperTransport traffic to SPI 4.2, Xaui and other mainstream communications interfaces. Taken together, HyperTransport links can more efficiently be used to transfer packet data from a framer to a security chip, for example.
The features will make processors using HyperTransport more useful in both control and data plane operations, particularly for low- and mid-range communications systems, said Brian Holden, chair of the consortium's technical working group and a principal engineer of PMC-Sierra.
High-end comms systems typically use proprietary data plane ASICs and interconnects.
Meanwhile, work continues in the consortium on a version 2.0 of the underlying physical layer of the spec, expected to “more than double” the current 1.6 Gbits/second data rates of the interconnect. Preparing the way for that spec, the new protocol upgrade also includes an error-retry protocol to bolster error correction capabilities of HyperTransport.
Intel Corp. is building similar packet-handling and peer-to-peer routing capabilities into its emerging Advanced Switching specification, a communications-centric variant of PCI Express. However, in Intel's case the work involves defining a new protocol for the Express physical layer spec. The AS spec is not expected to be finished until the end of this year.