SAN JOSE, Calif. A panel at the Fabless Semiconductor Association Suppliers' Expo here Thursday (Oct.9) looked into the issue of time to market from a number of angles, and concluded that, should it become a pressing matter, cooperation was the best way to attack it.
After panel chair James Hines, principal analyst at Dataquest, explored the traditional question of accelerating time to market, Dan Del Rosario, CEO of Photoronics, Inc. cut to the heart of the problem. "The problem is that time to market hasn't been an issue lately," Del Rosario stated. "Just the opposite. Because demand has been so soft we have had a shortage of designs moving through to tape out and production. That has hindered the learning curves for both mask making and fabs on new processes."
"Time to market is only an issue with leading-edge technology," agreed John Yu, vice president for process technology at TSMC. "It is not an issue at mature process nodes. Even 0.13-micron is pretty well worked out now and will go smoothly if the design is robust and the IP is silicon-proven."
Begging to differ just a bit, Scott Jewler, senior vice president in charge of assembly at Amcor Technology, pointed out that packaging had moved from the back of the bus to become a full-fledged time to market threat. "Packaging used to be an afterthought," Jewler observed. "But with the variety of packages available today, and with their impact on both electrical characteristics of the design and the reliability of the finished product, design teams are bringing in packaging engineers at the beginning, trying to identify packaging issues in advance, and working with the package supplier to co-optimize the package and the chip design."
The problem, Jewler said, was a business one rather than a technical one. He pointed out that there is no established business model for cooperation between the package supplier and the other players in the design chain. This tends to make a necessary step in the design flow either an act of generosity on the part of the package supplier or an ad-hoc joint development that must be negotiated for each design.
Don McMillan, vice president of engineering for analog tools at Synopsys, made a plea for deeper integration of tool chains and for one-stop shopping at Synopsys. He argued familiarly that the need to support hierarchy in the design and the need to support extensive reuse made the integration of point tools into the flow increasingly difficult, and that this pressure would eventually lead design teams to purchase entire tool platforms from a single tool supplier.
Asked if there were a way that leading-edge teams could overcome the apparently shallow learning curve that foundries experience with new materials, Yu responded that at 90 nm, TSMC at least was using no new materials at all. "There will be a learning curve at 90 nm," he said, "but it won't be new materials. We absorbed that learning at 130 nm. The learning this time will be ab out the all-new 300-mm equipment that we will be using for the 90 nm process."