iRoC Releases Robust SPARC Test Report Achieves 100% Transient Errors Protection for Logic and Memory
SANTA CLARA, Calif. and GRENOBLE, France - January 28, 2002 - iRoC Technologies, a leader in the field of electronic systems integrity, announced test results today that prove embedded intellectual property (IP) for error protection can be added to a system-on-chip (SoC) without decreasing high performance. iRoC’s error detection and correction in memories and logic circuits added no extra delay compared to the genuine die SPARC V8 and enabled memory reliability with a 100% efficiency of its specific robustness architecture. The conclusion is based on documented results of yearlong radiation tests on the iRoC Robust 32-bit RISC Processor, the Robust SPARC (code: ROC S81).
“We are making the results available to the industry to show the feasibility of preventing memory and logic failures in commercial ICs,” said Eric Dupont, president and CEO of iRoC Technologies Corporation. “Today our solutions can eliminate the vulnerability of electronic systems to transient errors which affect their availability and reliability. Hence, our Fault Tolerance Architecture in the chips increases MTTF of electronic systems.”
If and when systems fail because of signal integrity or radiation issues, it is not generally a deterministically predictable event, but a random failure and, therefore, may not be easy to pinpoint. Therefore, for applications requiring a high level of reliability such as high-end computing, secure networking systems and money transactions such as with SmartCards, such failures can be dramatic and costly.
Test Approach and Methodology
iRoC designed specific embedded Robustness IP blocks to track soft errors in processors. Originally designed by ESA (European Space Agency/LEON), a compatible SPARC V8 VHDL core was upgraded by iRoC for protection against transient faults occurring in memories and logic blocks. Specific iRoC code architecture was used for memories and innovative IP blocks have been implemented based on time redundancy methodologies for logic blocks. These embedded IPs provide self-correcting intelligence to observe signals at two different instances and compare them to filter out transient phenomena.
The associated robust netlist was manufactured using commercial 0.25ï¿½m process technology and the silicon was stressed under radiation attack, using the CYCLONE cyclotron facility of Louvain-la-Neuve in Belgium, to simulate soft errors inside. The genuine non-protected SPARC, LEON, was also manufactured to compare sensitivity. iRoC design engineering positioned at the front-end level process enables migration of the Fault Tolerant architecture to any other smaller geometries with a similar efficiency.
“I’ve reviewed the test results and am convinced that this approach offers designers the ability to achieve cost savings while bringing a protected system to market much faster,” stated Joseph Borel, a recognized expert in VLSI technology.
Silicon results strengthen the fact that these innovative, embedded Robustness IPs do not strap the SoC performance as simulation tended to prove. Robustness blocks in memories and in logic networks add no extra delay compared to the genuine die LEON. This test campaign accelerated the MTTF of the die and soft errors were observed in LEON, whereas no errors were noticed in the Robust SPARC. Thus, iRoC memory protection blocks enable designers to increase memory reliability with a 100% efficiency of its specific code architecture. Moreover, the most remarkable result is the detection and characterization of soft errors in logic blocks. Two key points stand out:
The logic network cross-section (see glossary below) is very close to the memory cross-section. That means for high-end systems using high frequency chips, logic had to be protected in the same way as memories.
A particle striking a node creates a transient pulse, similar to a logic signal, propagating through the logic network of which the width is hundreds of picoseconds depending on the energy: the pulse width range is from 500ps to 900ps.
This relative comparison between memory and logic questions the idea that only memory should be tested and protected against transient faults. In addition, the logic FIT rate is expected to increase due to other phenomenon such as cross coupling, ground bounce and delay faults. Finally, the FIT rate in logic is likely to be comparable to the FIT rate in memory.
Critical Need To Protect ICs From Transient Faults
Most of the time transient errors like soft errors or cross coupling effects are not fixed on silicon, and are not believed to create hard errors or system crashes at sea level. Memories are the first devices to be protected if any and logic networks are typically believed to be immune to 0.13 ï¿½m technologies. Logic blocks take much less area and are less susceptible to be hit by a strike. Soft error characterization, simulation and measurement tools have been focused on solutions for memories and not for logic blocks whose lack of protection comes more from a lack of tools and methodologies than from physics and design issues.
Obtaining the SPARC Test Report
The ROC S81 synthesis report will be available on iRoC web site by the end of January at www.iroctech.com.
FIT means “Failure In Time”. One FIT is one failure in 10E09 device-hours. Cross-Section: sigma =Number of error/(Fluence*Number of Bits) MTTF stands for Mean Time To Failure.
About iRoC Technologies
iRoC is an intellectual property (IP) provider in the semiconductor industry that embeds fault tolerance function into integrated circuits. The iRoC embedded Robustness IP family consists of cost-effective design solutions, customized for any application, to be integrated as the self-correcting intelligence of the chip and the final system. iRoC also provides a Robust IPs catalog. More information on the company's products and services can be obtained at www.iroctech.com.
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iRoC Technologies, Robust SPARC are trademarks of iRoC Technologies Corporation.