LONDON ARM Holdings plc's next-generation processor will be a superscalar machine that will break through the gigahertz clock frequency threshold that has until now blocked what is mainly the preserve of PC and server microprocessors, according to an ARM executive.
"The core will come out with lead partners during 2005 and be more broadly available at the end of 2005," Mike Inglis, ARM's executive vice president of marketing, said in an interview with Silicon Strategies. Inglis also confirmed that several of ARM's established licensees have been contributing to the next-generation core's specification.
The core is being targeted at the 65-nm manufacturing process node, although it will probably come out in a 90-nm process first, Inglis said.
Inglis declined to name the partners working on the ARMXX company executives are still deciding whether it should be called ARM12. But Inglis did describe the partners as being in the "first division" of ARM's licensees.
Work on the new core started about six months ago and much of the heavy lifting has been completed, Inglis said. "We've thought about the architecture, we've partitioned it. We're moving towards the microarchitecture," he said.
All of ARM's processors, including those based on the popular ARM7, ARM9 and ARM11 inner cores, have been single-issue machines, Inglis confirmed, so a move to a superscalar machine, that can issue multiple instructions per cycle would be break with the past for ARM.
In other respects, such as retaining code compatibility with previous cores, and pursuing power-efficiency, ARMXX is expected to remain true to its heritage.
Inglis did not say whether the next-generation core would be the subject of a revision of the instruction set architecture, which has reached version 6.
The ARMv6 architecture, announced in 2001, features single instruction multiple data (SIMD) extensions to increase processing performance. The first core to meet ARMv6 is the ARM1136J(F)-S.
"We need to go to the next level of performance in the ARM architecture for mobile applications," Inglis said, emphasizing that the performance of the next-generation core could not be obtained at the expense of power efficiency.
One technical issue is whether a superscalar machine can be compatible with reduced instruction set computing (RISC) principles. These principles primarily relate to keeping the design simple and developing instructions for the most frequently used programming constructs that execute in a single cycle.
"We don't believe what we've got fundamentally does break with RISC," said Inglis. "The question is what are people going to want to do on a mobile platform in 2005. It's not going to follow the PC model," he said. "We've seen how camera phones have taken off in Europe. But in Japan you see much more media- rich machines."
Inglis said the next-generation core is one arm of a dual-pronged attack on embedded applications the other being multiprocessing, the subject of an announcement with NEC Electronics earlier in the week.
"Multiprocessing is very interesting to ARM and another way of solving the problem. You can either use extra processors to increase performance, or you can get the equivalent performance at lower power."
Inglis said NEC has a done much work in parallel processing and that approach could yield design wins for ARM in digital consumer, automotive multimedia and other tethered applications.
"The uniprocessor roadmap always goes up and to the right, and we're not going to bet against that but multiprocessing may be a technology solution," Inglis said.
"After about 2006 the uniprocessor versus multiprocessor argument may become more of a 'religious' debate. We have to see what religion the world comes to believe in at that point. And it may be different by geography and by application, but we need to be in a position to support what customers want."
Inglis added: "Mainstream wireless i s uniprocessor for ARM. In the future it may be uniprocessor or it may be multiprocessor from ARM."
However, academic theory and existing experience with multi- and massively parallel processing suggests that reusing conventional uniprocessor instruction sets is not an optimum solution. Should ARM be trying to build a parallel processing edifice around established ARM cores?
"You may need to do some rearchitecting for multiprocessing but you don't need to throw the instruction set away," Inglis responded.