LONDON Cognigine Corp., a network processor startup, is scheduled to present details of its Variable Instruction Set Communications (VISC) technology at the Network Processor Forum in San Jose this Thursday (June 14).
The architecture is an innovative combination of elements from various historical approaches to computing and is expected to produce a 200-MHz chip that can handle Layer 2 to Layer 7 software tasks and handle 25 megapackets per second.
Each processor or reconfigurable communications unit (RCU) in Cognigine's distributed multiprocessor is embedded into a hierarchical switching fabric that gives each RCU access to generalized communications. But at the individual RCU level, Cognigine employs various approaches to maximize performance.
"It is a kind of hybrid," said Nick Kucharewski, president and chief executive officer of Cognigine (Fremont, Calif.). "Some instructions are VLIW-like, some of its approaches are SIMD [sing le instruction multiple data]. It does look like a multi-issue machine." The variability doesn't reflect a jumping between different instructions sets, but rather the use of an instruction cache that points to a dictionary of parameters, Kucharewski said.
Cognigine expects its network processor to find deployment both at the "backbone" and "metropolitan core" interconnection points, and at the metro core-to-metro access points, Kucharewski said.
Ideally software programmability would provide wire speeds of 10 Gbits/second, which have been historically associated with dedicated ASICs, Kucharewski said.
Programmability comes by way of a C language compiler and an intermediate application library. "The user would not see the variable part of VISC," Kucharewski said. "The I-cache [instruction cache] points to the dictionary which sets things such as bus width and numbers of operands. VISC is really reconfiguration of the pipeline on a cycle-by-cycle basis."
Four five-stage 64-bit pipelines are included in each RCU. These basic processors include instruction and data memories.
The architecture then links four of these with a non-blocking switching fabric. And these larger blocks are then linked again in a hierarchical structure.
Cognigine plans to put 16 RCUs on a chip, but said the architecture scales well because of the modularity of the switching fabric.
"The entire chip is memory mapped, so that to any RCU any other RCU simply looks like memory," Kucharewski said, who called the part a packet-based network on a chip.
Cognigine is entering a sector of the electronics industry that is quickly becoming crowded, but Kucharewski said he believes Cognigine is in good shape. With software programmability at 10-Gbit/s speeds, new equipment designs can be done in days rather than months, which would be required for a multichip ASIC design.
"We are getting close to tape out," he said. "We expect to be able to sample in the fourth quarter."
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