Soft processors were once dismissed as the poor man's MPU-low in cost with performance to match. But as momentum builds toward multiprocessor chip designs, these user-configurable engines are getting a closer look.
Ready to catch the next wave, Tensilica Inc. is unveiling its fourth-generation synthesizable MPU core, Xtensa IV, which contains architectural hooks to support the use of three or more processors in an ASIC and the ability to repartition instructions up to the point of manufacturing.
Just about every network processor on the market today uses a multiprocessor architecture, according to analyst Linley Gwennap at the Linley Group, Mountain View, Calif. But system designers don't have much flexibility beyond using a single, fixed CPU and a DSP, or a pure gates implementation, said Stephen Roddy, director of product marketing at Tensilica, Santa Clara, Calif.
"The likelihood in the future of 10, 20, or 30 processors on an ASIC being the norm is pretty high," Roddy said. "But the established architectures were built in the days when you put one processor down in a design. Are they efficient for multiprocessor designs? Probably not."
Tensilica claims its 200MHz Xtensa IV is up to the task and cites as proof a recent design win in Hughes Network Systems' Spaceway broadband satellite set-top boxes. Previously, HNS said it standardized on MIPS Technologies Inc.'s architecture, but changed its mind.
HNS plans to use numerous Xtensa cores in its chip designs, each tuned to a specific task. To do this and meet the market window requires MPU cores that not only meet HNS' performance specs, but are easy to configure and verify, said Dan Fraley, senior vice president of engineering at the Germantown, Md., OEM.
"The ability to mold the processor to suit the application, rather than mold the application around a fixed processor, is powerful," said analyst Cary Snyder at MicroDesign Resources in San Jose.
The Xtensa IV architecture is designed to allow users to add custom instructions and hardware execution units, and automatically generate software development and system modeling tools.
Among its features is the 128-bit wide Xtensa Local Memory Interface, which can be used to connect Xtensa processors in parallel, or integrate existing state machine logic into Xtensa's memory.
Tensilica also offers a multiprocessor debugging environment that allows users to easily transition from software simulation to actual hardware debugging using a consistent GNU-based tool chain.
Single-use licenses start at $350,000.