San Jose, Calif. — October 27, 2003 — LogicVision, Inc. (NASDAQ: LGVN), the leading provider of embedded test solutions, announced today a new automation tool to guide designers through the embedded test integration process. ET PlannerTM, developed in conjunction with Atrenta Inc., the leading provider of predictive analysis technology, is used at the Register Transfer Level (RTL) design stage and provides upfront guidance and compatibility verification between the design architecture and LogicVision’s embedded test technologies. LogicVision believes this expert guidance will help ensure a successful integration process.
To reduce the chance of design iteration, LogicVision and Atrenta have jointly developed a new capability that is intended to eliminate any unpredictability of the embedded test integration process by providing upfront architectural verification at the RTL level. This new capability along with existing RTL level LogicVision DFT rule checking is packaged into one new tool, ET Planner, included in LogicVision’s latest product LV2004. Designers can now make architectural decisions early in the design flow to enable the design to be optimized for embedded test. This upfront verification is expected to reduce or eliminate any costly and time-consuming design iterations later in the development cycle. Use of the ET Planner tool is also expected to help to ensure that the RTL code is kept synchronized to lower level netlist representations.
“Test is becoming a major concern with companies that are now developing more hierarchical designs with narrower geometries of 90 nanometers and less,” stated Dr. Vinod K. Agarwal, president and CEO of LogicVision. “We believe our integrated solution with Atrenta will help achieve the integration of embedded test during the design phase so that the quality and cost advantages can be achieved downstream.”
“We are pleased to work with LogicVision to create an innovative and powerful solution for embedded test developers,” said Dr. Ajoy Bose, Atrenta’s chairman, president and CEO. “We believe ET Planner will enable LogicVision users to verify that their RTL design architecture meets the requirements for embedded test integration and will help prevent costly and time consuming iterations late in the development cycle.”
Availability, Pricing, and Distribution
The LV2004-ET Planner tool will be available beginning of 2004 for Linux, Solaris and HP-UX operating systems. ET Planner will be bundled with all Memory BIST and Logic BIST packages. For more product details and pricing, please contact us.
About LogicVision Inc.
LogicVision (NASDAQ: LGVN) provides proprietary technologies for embedded test that enable the more efficient design and manufacture of complex semiconductors. LogicVision's embedded test solution allows integrated circuit designers to embed into a semiconductor design test functionality that can be used during semiconductor production and throughout the useful life of the chip. For more information on the company and its products, please visit the LogicVision website at www.logicvision.com.
FORWARD LOOKING STATEMENTS:
Except for the historical information contained herein, the matters set forth in this press release, including statements as to the expected benefits of LogicVision’s Embedded Test technology and the LV2004-ET Planner, including benefits in the integration process during the design phase, quality and cost advantages and time savings, the expected availability of the LV2004-ET Planner, and expectations regarding the adoption of embedded test, are forward-looking statements within the meaning of the Private Securities Litigation Reform Act of 1995. These forward-looking statements are subject to risk and uncertainties that could cause actual results to differ materially, including, but not limited to, the impact of competitive products and technological advances, and other risks detailed in LogicVision's Form 10-Q for the quarter ended June 30, 2003, and from time to time in LogicVision's SEC reports. These forward-looking statements speak only as of the date hereof. LogicVision disclaims any obligation to update these forward-looking statements.
LogicVision, Embedded Test, LV2004, ET Planner, Logicvision Ready and LogicVision logos are trademarks or registered trademarks of LogicVision Inc. in the United States and other countries. All other trademarks and service marks are the property of their respective owners.