San Jose, CA – October 21, 2003
- Modelware, a leading provider of Semiconductor Intellectual Property (SIP) for telecom and networking applications, today announced the availability of the PluriBus™ iUniversal core, a unified bus interface implementation capable of operating in ATM or packet mode at rates ranging from 155 Mbps to 2.4 Gbps and higher. The iUniversal core implements several bus protocols including UTOPIA L2, UTOPIA L3, POS-PHY L2 (PL2), and POS-PHY L3 (PL3)/SPI-3, all in both Physical and Link Layer modes.
Modelware’s iUniversal core fully complies with the ATM Forum (UTOPIA 2/3), the Saturn Group (PL2/3), and the Optical Internetworking Forum (SPI-3) standards. In addition, the iUniversal core has several micro-configuration options that allow small, local variations from the standard operation to create other proprietary bus protocols or to ensure interoperability with devices that deviate from the standards’ operation.
The iUniversal core is ideal for devices that need to interface to multiple rates and protocols such as Network Processors and Traffic Managers. Modelware will also use the iUniversal core in the SmartBridge™ family of products to implement highly configurable bridges that multiplex/de-multiplex data from multiple sources with different rates and protocols into a single high-speed pipe.
“The sophistication of the iUniversal core is a result of our experience with three generations of bus interfaces that have been used in a number of wide-ranging applications.” said Anthony Dalleggio, VP of Marketing at Modelware; “The flexibility provided by this core allows users to support multiple applications with the ease of a single design.”About Modelware’s PluriBus iUniversal Foundation and Manager Cores
Modelware’s iUniversal core uses a single engine implementation resulting in a size that is significantly smaller than the combined size of the individual cores for all the protocols. The iUniversal Foundation core is used in implementations that do not require per-channel buffering or ones where channelized buffering is implemented elsewhere in the system. In addition to the functions provided by the Foundation core, the Manager core implements per-channel buffering and flow control, and data transfer scheduling. Both cores are delivered in a ready-to-use package including a comprehensive test environment, synthesis scripts, and device layout guidelines.About Modelware, Inc.
Modelware is a leading provider of Semiconductor Intellectual Property (SIP) cores for telecom and networking ASIC and FPGA applications. Its highly scalable products provide semiconductor and system OEM customers a compelling value and enable them to bring standards-compliant products to market faster. Modelware also offers standard bridging products that provide interoperability solutions between different interface standards. By offering design services that complement its standard product offering, Modelware provides customized solutions that exactly match the customer’s application. Modelware’s products and services are backed with an exceptional level of support that is available to customers throughout their product design cycle.
For more information, visit www.modelware.com.###
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