Companies Define Verification Process Automation (VPA) Landscape and Common Data Models
MOUNTAIN VIEW, Calif.--(BUSINESS WIRE)--Nov. 3, 2003-- Verisity Ltd. (Nasdaq:VRST), 0-In Design Automation and Novas Software, Inc. today announced a strategic collaboration to tackle verification challenges at nanometer geometries with Verification Process Automation (VPA) solutions that will dramatically increase the productivity, quality, predictability and resource utilization of complex verification projects. The three companies will initially focus on 90-nanometer, 50-plus million gate, multi-CPU and embedded software designs with well-defined processes that span the entire system-on-chip (SoC) verification flow, from the module to the unit, chip, system and project-level.
VPA offers the potential of 10x improvements throughout the verification flow with well-defined processes that simplify verification, from executable plans to total coverage of hardware and software functionality to verification closure. In support of this, Verisity, 0-In and Novas are collaborating to define nanometer VPA flows and interfaces within their specialized areas of expertise. As part of this strategic collaboration, the companies will also jointly define common data models to enable critical process information to be shared by multiple best-in-class solutions that will spur innovation in new areas of distributed verification management and enable further productivity gains through synergies between SoC verification flow components.
Specifically, Verisity will define the top down, spec-driven verification management process, starting from an executable verification and coverage metric plan, to the composition of a multi-level verification environment for unit, chip, and system-level verification. Verisity will also provide a process to manage the distributed verification activities towards total coverage and closure.
"Many leading-edge companies doing 90-nanometer SoC designs are shooting in the dark, without a verification plan, or a clear view of what is yet to be accomplished and how, or where, to apply their next verification cycle," said Steve Glaser, vice president of corporate marketing and business development for Verisity. "VPA solutions must provide visibility, control and new levels of automation to a much broader and highly distributed verification process. This process touches the system architects, hardware designers, software designers and verification specialists who must bring it all together. This strategic collaboration is the first of its kind, enabling the industry to solve the real challenges of nanometer IC and system-level verification."
0-In will define the implementation-centric "design-for-verification" flows, incorporating assertion-based and formal verification. Assertions link the design implementation with the specification and may span multiple levels of abstraction. 0-In will provide two key processes, one focused on verification hotspots that are verified completely with exhaustive formal verification techniques, and the second focused on critical coverage points in a design that can be monitored with assertions in dynamic verification. These processes are critical for platform-based design and verification reuse, which are key elements of nanometer SoC verification.
"We help our customers achieve productivity improvements that allow them to reach verification closure sooner by providing the tools, methods and processes that address their hardest verification problems," said Steve White, 0-In's CEO and president. "This collaboration with Verisity and Novas combines our processes with other best-in-class verification solutions to make the total coverage model a reality and to help move customers even closer to automated verification throughout the design flow."
Novas will define the debug and failure analysis flows spanning the entire top down, spec-driven and implementation-up range of activities, from signal to transaction level. Leveraging debug automation technologies, Novas will enable the rapid detection of the root causes of issues, eliminating much of the manual tracking procedures used today. By focusing on fast design behavior comprehension, these flows will allow designers and verification specialists to quickly close the loop on design flaws, reducing the engineering effort traditionally involved.
"Improvements in EDA tool speed and capacity are not enough to address the complex verification challenges of leading-edge 90-nanometer designs. What's needed is more specialized automation directed at the most significant process bottlenecks," said Dave Kelf, vice president of marketing at Novas Software, Inc. "We've seen this work with Novas' focus on automating engineering-intensive debug activities. Industry collaborations like this extend the concept of verification process automation, and expand the core tool flow to deliver greater productivity benefits for advanced design methodologies."
The group's VPA solutions are aimed at overcoming the huge number of verification challenges identified by nanometer development teams, including:
a) Limited verification expertise, Infrastructure vs. Process Automation
b) Scarce human and compute resources that are often underutilized,
c) A lack of metrics to guide and improve the predictability of processes,
d) A confusing spectrum of approaches to verify certain properties or functions at different levels in the chip hierarchy,
e) Interdependencies of hardware and embedded software verification activities,
f) An overload of data resulting from multiple types of interdependent failure and coverage databases, and,
g) Distributed verification activities that must be managed across geographical and even corporate boundaries.
Functional verification is the number one bottleneck in the nanometer IC development cycle, consuming as much as 70 percent of the entire design cycle. Incomplete verification is the source for 50 to 75 percent of all respins, which typically cost millions of dollars and several months of lost engineering manpower at 90-nanometer geometries. As design complexity continues to increase, improvements to verification infrastructure alone is proving to be insufficient. Simulator performance has capped out and can no longer keep pace with the growing verification gap that is especially acute with nanometer-scale designs.
In contrast, Verisity, 0-In and Novas are focused on verification processes that automate best practices to create new levels of productivity, quality, predictability and resource utilization. These companies are focused on various elements of VPA, covering all processes from the module, to the unit, chip, system, and project-level, spanning both hardware and software.
Each of the companies' VPA solutions have key components that include a process/methodology, reusable verification IP, verification specification and environment development aids, coverage generation via both static and dynamic methods, exhaustive formal methods and failure analysis and debug. In addition, these solutions will utilize the appropriate verification infrastructure such as, HDL simulation, C/SystemC-based simulation, acceleration, emulation, FPGA prototypes and/or real silicon devices.
Common Data Models
The companies intend to utilize common data models from which their best-in-class VPA solutions will work. The three companies believe that common data models will enable each tool to work with the latest and most complete set of information, including but not limited to:
a) The verification plan that specifies what needs to be verified,
b) Resources, including tools, servers, licenses, etc.,
c) Specific run data, statistics and log information,
d) Coverage model, including functional, structural, assertion and code coverage aspects, as well as coverage goals for each aspect,
e) Actual coverage and trace results for verification runs whether simulation based or formally verified,
f) Information about failed runs, including failure analysis and regression,
g) Relations between data items, for example relating some specific runs to a specific failure for the purpose of failure analysis.
A VPA flow based on common data models will make it easier to quickly adopt best-in-class solutions, as well as create new possibilities for innovation. In particular, internal or third-party tools (e.g., proprietary formal tools, dependency management or requirement traceability tools) will also be able to read and use the same data to further enhance the verification process. By combining VPA approaches, new levels of automation will be possible (e.g., static with dynamic engines, random with directed or real-world testing and monitoring) as well as yield more optimal, scalable results.
Verisity, Ltd. (Nasdaq:VRST), is the leading supplier of process automation solutions for the functional verification market. The company addresses customers' critical business issues with its market-leading software and intellectual property (IP) that effectively and efficiently verify the design of electronic systems and complex integrated circuits for the communications, computing, and consumer electronics global markets. Verisity's VPA solutions enable projects to move from executable verification plans to module, unit, and chip/system level "total coverage" and verification closure, while maximizing productivity, product quality, and predictability of schedules. The company's strong market presence is driven by its proven technology, methodology, and solid strategic partnerships and programs. Verisity's customer list includes leading companies in all strategic technology sectors. Verisity is a global organization with offices throughout Asia, Europe, and North America. Verisity's principal executive offices are located in Mountain View, Calif., with its principal research and development offices located in Rosh Ha'ain, Israel. For more information, visit www.verisity.com.
0-In Design Automation, Inc. (pronounced "zero-in") develops and supports functional verification products that help verify multi-million gate application-specific integrated circuit (ASIC) and system-on-chip (SoC) designs. The company delivers a comprehensive assertion-based verification (ABV) solution that provides value throughout the design and verification cycle -- from the block level to the chip and system level. Twelve of the 15 largest electronics companies have adopted 0-In tools and methodologies in their integrated circuit (IC) design verification flows. 0-In was founded in 1996 and is based in San Jose, Calif. For more information, see http://www.0-in.com.
Novas is the pioneer of debug systems that reduce the functional verification costs for complex IC designs. Building upon the strength of its market-leading Debussy(R) Debug System, Novas' Verdi(TM) Behavior-Based Debug System further improves the efficiency of designers in the system-on-chip era with advanced design exploration and automated debug capabilities. These allow design teams to better understand and analyze complex or unfamiliar design behavior, and cut by half or more the time it takes to locate, isolate and solve the root causes of design problems. With more than 10,000 systems in use today worldwide, Novas has for two consecutive years received the highest ranking for customer satisfaction in a comprehensive EDA study published by CMP. Novas is headquartered in San Jose, Calif. with offices in Europe, Japan and Asia-Pacific. For more information, visit www.novas.com.
Verisity, the Verisity logo, and Specman Elite are either registered trademarks or trademarks of Verisity Design, Inc. in the United States and/or other jurisdictions. 0-In(R) is a registered trademark of 0-In Design Automation, Inc. Debussy is a registered trademark and Verdi is a trademark of Novas Software, Inc. All other trademarks are the property of their respective holders.
SOURCE: Verisity Design, Inc.