Lightspeed restructures on IP model
By Ron Wilson and Crista Souza, EE Times
November 3, 2003 (10:53 a.m. EST)
SAN MATEO, Calif. Struggling Lightspeed Semiconductor (Sunnyvale, Calif.) puts to rest months of rumors with the announcement today that it will no longer seek new customers for its structured ASICs. Instead, the company is preparing to license its metal-mask programmable-logic fabric as intellectual property to other semiconductor vendors and directly to design teams.
The move, coming from one of the pioneers of the emerging structured-ASIC market, raises questions about the viability of the product segment. But other industry players say their products are finding acceptance, even as Lightspeed changes its business model.
Research firm In-Stat/MDR (Phoenix) pegs the structured-ASIC market at $30 million this year, with growth to $760 million by 2007, according to analyst Jerry Worchel. And that picture is backed up by various vendor reports from the field.
"We are definitely seeing traction for the concept," said Doug Ba iley, vice president of marketing at Chip Express Corp. (Santa Clara, Calif.). The company is seeing 10 percent quarter-on-quarter revenue growth, Bailey said. In addition, its book-to-bill ratio hit 1.6 in the third quarter and is likely to be near 1.2 in the fourth quarter.
"The encouraging thing for the long term is that big companies are starting to vet structured-ASIC vendors specifically," Bailey said. "We have people calling and asking for structured ASICs for a portion of their planned ASIC designs next year."
Other vendors related similar experiences. AMI Semiconductor Inc. (Pocatello, Idaho) reported 18 percent growth in its structured products between the second and third quarters. NEC Electronics America Inc. (Santa Clara, Calif.) also has seen significant growth, according to NEC associate vice president and general manager Phillip LoPresti. "We are starting to see RFQs specifically asking for structured devices," he said.
And Fujitsu Microelectronics America Inc. (San J ose, Calif.) reported that customer acceptance of its AccelArray has been so rapid that the company is expanding the staff of the structured products group to support the designs.
That enthusiasm contrasts strongly with Lightspeed's situation. Michael Sydow, Lightspeed's vice president of marketing, said the company possesses a unique technology for building structured ASICs that has been refined by several years of actual market experience and that is well-regarded by users. But chip sales were not extracting the true value from the technology, he said.
"Part of the issue was the high cost of moving the technology to 0.13 micron," Sydow said. "But as the market has tightened, we have seen companies narrowing their supplier lists and often simply refusing outright to do business with small companies. We were winning design-ins in the engineering department and then being vetoed in purchasing."
Lightspeed management concluded that the company was simply too small to stay in the ASIC bu siness. But it made no sense to abandon a commercially successful architecture, Sydow said.
So Lightspeed is changing its approach. While it will continue to provide chips to existing customers possibly in conjunction with a partner it will no longer seek ASIC design wins. Rather, Lightspeed is packaging its fabric design, proprietary tools and market experience into an IP offering.
That offering will be two-pronged. First, Lightspeed will provide complete ASIC base wafer and tool chain packages and license them to ASIC companies that wish a quick, proven entry into the structured-ASIC market. Sydow said discussions are already advancing with at least one such ASIC supplier.
| Under its revised strategy, Lightspeed will provide base wafers and license a propriet ary structured-ASIC design flow. |
Second, the company is tuning its design tool flow to merge it seamlessly with a traditional, cell-based design flow. That will allow Lightspeed to license an ASSP vendor or OEM using a customer-owned-tooling design flow to embed rectangular regions of Lightspeed's structured-ASIC fabric directly into other cell-based designs for inclusion in a set-top-box system-on-chip, for example.
Initially, the tool chain will be the one Lightspeed currently uses in mapping customer designs into its Luminance product line. Under such an arrangement, Lightspeed would consult with the customer, create a fabric module to meet the customer's requirements and then provide the GDSII files, integration information and simulation models necessary for the customer to include the module in its own chip. Lightspeed would also provide access to its design mapping software and support services.
The company is also working on a streamlined tool, h owever, that will permit the customer itself to do placement and routing of designs into Lightspeed logic tiles and to complete design closure. The tool, called Design Builder, is expected to be available internally to Lightspeed engineers by February and to be robust enough for customer use by the end of 2004.
"This is an opportunity for designers to include modules of metal-mask configurable logic in their designs without having to go through the learning curve that we have been through already," said Lightspeed chief technical officer Eric Dellinger. "We have the design-mapping tools. We have learned the lessons about how to achieve routability to get 75 percent of the density of cell-based design. We have learned, from lots of designs, the architectural aspects of building an array of complex tiles. We understand power and clock routing for these architectures, and we know how to achieve full testability. And we have the patent portfolio to protect our learning.
"These are not things tha t come cheaply or quickly to a novice in the metal-configured array area."
Thus Lightspeed, while not directly playing in the ASIC game, may profit by helping others join the party.