San Jose, California, November 6, 2003 -- eASIC Corporation, a provider of configurable Structured ASIC technology, today announced that it has been issued one additional patent titled “Customizable and programmable cell array” (6,642,744) by the United States Patent and Trademark Office. This patent applies to eASIC’s unique technology of innovative configurable fabric, which combines FPGA-like logic programmability (SRAM-LUT) with Standard Cell-like metal routing, and it complements the other 7 patents granted to eASIC. Moreover, this technology allows eASIC to offer a breakthrough configurable logic fabric with NRE-less/Mask-less customization, when using Direct-Write eBeam. As only a single Via layer (Via 6) is used for customization, versus other methods that require writing several customized metal layers, eASIC’s technology enables very efficient and high-throughput Direct-write eBeam lithography.
This hybrid of FPGA and Standard Cell, presents a unique approach to Structured ASIC, combining bit-stream programmable cell array (LUT) with a single via layer customizable routing. Dubbed Structured eASIC, this technology serves as the foundation for the company’s products, aimed at dramatically lowering the tooling cost and shortening the turnaround time of ASIC, System-on-Chip and Platform-based designs, while maintaining high performance. Through its re-programming capability and efficient interchange between logic gates and memory bits, eASIC’s approach features higher flexibility and ease-of-debug compared to cell-based ASIC. And through its customized interconnection approach, eASIC provides lower production unit cost and higher performance compared to FPGA.
“Our granted patents have very broad and fundamental claims, and we are pleased with this recognition of eASIC’s breakthrough technology,” said Zvi Or-Bach, eASIC President and CEO. “This powerful IP protection supports our business strategy of offering embedded configurable logic IP for the high-end ASSP market, as well as of building an ultimate configurable logic array for the Structured ASIC market, together with strategic partners. eASIC’s technology is the only solution that can provide no-NRE ASIC together with low production unit cost and high performance. We strongly believe that with this type of technology, the number of new ASIC designs will rise again and emerging applications can flourish”.
eASIC’s fabric can be configured as logic, PLD or dual-port SRAM, and is deployed in two implementation options:
- Embedded IP Core – eASICore: configurable logic cores, licensable for
System-on-Chip and platform-based designs
- Structured eASIC: complete arrays of eASIC fabric, being developed with
partners to include the relevant I/Os, block memories, clock distribution, etc.
eASIC® has developed a breakthrough Structured ASIC technology aimed at dramatically reducing the overall fabrication cost and time of customized high performance semiconductor chips, efficiently utilizing standard manufacturing processes. By innovative use of proven logic programming together with efficient metal routing, eASIC’s technology enables rapid and low-cost ASIC design, as well as cost-effective customization of System-on-Chip and platform-based designs. With its unique technology, which was successfully proven in silicon and validated by customers, the company is positioned to become the preferred ASIC solution, targeting the emerging Structured ASIC market, which is defined as the gap between FPGA and Standard Cell.
eASIC Corporation is a privately held company, founded In 1999 by Zvi Or-Bach, the founder of Chip Express. Headquartered in San-Jose California, eASIC holds a highly skilled and motivated engineering and R&D team in Romania.