Assertion compiler enables industry-wide assertion interoperability
SAN JOSE, Calif. -November 10, 2003 - Today 0-In Design Automation, the Assertion-Based Verification Company, announced the availability of its enhanced assertion compiler, the industry's only multi-language assertion synthesis tool. 0-In's assertion compiler is one component of the 0-In Assertion-Based Verification (ABV) Suite and builds on the standardization work of IEEE and Accellera to provide the industry's most comprehensive interoperability strategy for assertions and formal verification.
"Our interoperability approach recognizes that customers often want to specify their assertions with a variety of languages and libraries, and then be able to use these assertions in multiple simulation, formal verification and hardware verification tools without having to re-specify," said 0-In president and CEO Steve White. "They also want additional value from these assertions, such as coverage, management and ease-of-use."
The 0-In assertion compiler protects the investment that companies make to use assertions in their functional verification flows by giving design teams the flexibility to use any of the emerging assertion formats with any RTL functional verification tool. Design teams are free to choose the best tools for their needs independent of their selected assertion format. This speeds up the verification cycle and enables greater reuse of core blocks and third-party IP. In addition, the assertion compiler adds value to raw assertions specified with an assertion language by adding coverage metrics and providing management capabilities.
Assertion Synthesis Provides Interoperability
The 0-In assertion compiler provides multi-way interoperability between various assertion formats and various verification tools. It accepts assertions in any of the five popular and standard formats available now or in the near future. These formats are:
- Accellera's Property Specification Language (PSL)
- Accellera's SystemVerilog Assertions (SVA)
- IEEE-1364 Verilog
- Accellera's Open Verification Library (OVL)
- The 0-In CheckerWare® library (CW)
The 0-In assertion compiler reads in assertions in any of these five formats and synthesizes HDL assertions in a format that can be used in any third-party simulator, formal verification tool, hardware-assisted verification box or even FPGA prototyping system. This allows assertions written in PSL or SVA to be usable by tools that do not directly accept these formats. Designers can adopt any of the emerging standards without fear of being locked into any particular verification tool vendor.
Interoperability Critical for Reuse, IP and SoC Productivity
The ability to verify assertions specified in different formats and use them all in any verification engine is especially critical for projects that reuse design blocks, design with third-party IP or design system-on-chip (SoC) devices. In these situations, different teams may have chosen to use different assertion formats and/or different verification tools. To complete verification, it is necessary to interoperate between the different formats. The 0-In assertion compiler provides this capability.
"In the current assertion standards environment, interoperability is a mandatory requirement when selecting verification tools," added Mr. White. "0-In understands the importance of protecting our customers against the uncertainty and the inevitable evolution that will occur. Our customers need to tape out now and can't wait for the standards to settle. 0-In will make sure their verification investment is protected going forward."
Assertion Synthesis Adds Value to Assertion Standards
In addition to providing interoperability between the different assertion standards, the 0-In assertion compiler adds value to the standards languages and verification IP libraries. The 0-In CheckerWare library contains structural coverage information, management tools and infrastructure for ease-of-use on top of the assertion checking it provides. The assertion compiler adds many of these capabilities to raw assertions specified in the Accellera and IEEE formats.
"Our customers value the combination of assertions and structural coverage to provide easy to use metrics about their verification progress. Naturally they wanted these benefits for all of their assertions, regardless of specification method," said Mr. White. "We believe that a unified, integrated view of coverage and assertions is the only way for teams to reach verification closure."
Unified structural coverage is currently shipping with the 0-In ABV suite. It provides users with three important metrics:
- Static structural coverage measures whether there are enough assertions in a design
- Simulation structural coverage measures whether corner-cases are covered
- Formal structural coverage measures how well formal verification has analyzed corner cases
In addition to metrics, productive use of assertions requires links to debugging tools and management tools. The 0-In assertion compiler utilizes the 0-In View assertion management capability and links with best-in-class partner debugging tools, such as those from Novas.
What Partners Are Saying About Assertion Synthesis
"The Cadence® Incisive™ verification platform is based on open standards," said Victor Berman, group director of language and IP strategy at Cadence Design Systems, "We've worked with 0-In, a member of the Cadence Connections® Program, to ensure that their assertions work well within Incisive, so that our joint customers enjoy the fastest, most efficient verification. We applaud 0-In's continued commitment to open interoperability, including their support of Verilog, VHDL, SystemVerilog, PSL and OVL."
"Assertion-based verification enables more efficient detection of design issues, and is becoming a key component of advanced debug methodologies," noted Dave Kelf, vice president of marketing at Novas Software, Inc. "With our mutual support for multiple assertion formats, engineers can leverage the interoperability between 0-In's technology and Novas' assertion-driven debug capabilities for a more complete verification platform that enhances their ability to understand and correct design behavior. "
"Verisity and 0-In are working together to provide an integrated verification process automation solution for our combined customer base," said Steve Glaser, vice president of marketing and business development for Verisity. "We believe that in order to break through the functional verification bottleneck, customers require best-in-class point solutions that cover the module level through the unit, chip, system and project levels. True interoperability means that customers have freedom of choice and vendors stay motivated to innovate."
Availability, Packaging and Pricing
The 0-In assertion compiler is bundled with all products in the 0-In ABV suite. Support for the different standards will roll out over time. Verilog, OVL and 0-In CheckerWare are currently supported. PSL will be supported starting in V2.1 of the 0-In ABV suite, scheduled for release in Q4 2003, with further enhancements planned for V2.2 in Q1 2004. SVA support is planned for 1H 2004, pending support from simulators.
0-In Design Automation, Inc. (pronounced "zero-in") develops and supports functional verification products that help verify multi-million gate application-specific integrated circuit (ASIC) and system-on-chip (SoC) designs. The company delivers a comprehensive assertion-based verification (ABV) solution that provides value throughout the design and verification cycle - from the block level to the chip and system level. Twelve of the 15 largest electronics companies have adopted 0-In tools and methodologies in their integrated circuit (IC) design verification flows. 0-In was founded in 1996 and is based in San Jose, Calif. For more information, see http://www.0-in.com.
0-In® and CheckerWare® are registered trademarks of 0-In Design Automation, Inc.