ORSPI4 FPSC offers two low-power embedded SPI4.2 cores, 4 channels of 3.7 Gbps SERDES, embedded QDR II memory controller plus 16K field programmable logic elements
HILLSBORO, OR - November 17, 2003 - Lattice Semiconductor Corporation (NASDAQ: LSCC), the leader in programmable SERDES technology, today announced the availability of the ORSPI4, a Field Programmable System-on-a-Chip (FPSC) that efficiently integrates ASIC and FPGA technologies. By combining the two approaches, Lattice has developed a more highly integrated, higher performance, lower cost and lower power SPI4.2 solution when compared to a full FPGA implementation. The pre-engineered ASIC block on the ORSPI4 contains two SPI4.2 interface blocks, a high-speed Quad Data Rate (QDR II) SRAM memory controller, 4 channels of 600 Mbps to 3.7 Gigabits per second (Gbps) SERDES, 8b/10b encoding/decoding and other supporting logic. Connected to the ASIC block is a high performance FPGA with over 16,000 FPGA logic elements plus embedded block RAM. The ORSPI4 FPSC is the world's most highly integrated field programmable System-on-a-Chip targeted at line card applications for high-speed communications systems in the Metro space.
"The ORSPI4 FPSC is the tenth FPSC product that Lattice has introduced into the market, but the first targeted specifically at a growing line card segment," said Stan Kopec, vice president of corporate marketing at Lattice. "Analysts expect line card shipments to rise from 1.9 million ports in 2002 to 4.8 million ports in 2006, a 27% compound annual growth rate (CAGR), and Lattice will be there with a highly-integrated device that will bridge network processors, MACs and framers to high-speed serial backplanes," added Kopec.
SPI4.2 (System-Packet Interface, Level 4, Phase 2) is a recent system-level interface standard that enables the development of flexible, scalable systems for a converged data and telecommunications infrastructure. Published in 2001 by the Optical Internetworking Forum (OIF), the SPI4.2 standard supports the transmission of multiple protocols at variable, high-speed data rates, including: Packet-over-SONET/SDH (POS), OC-192, Ethernet, Fast Ethernet, Gigabit Ethernet, 10 Gigabit Ethernet, and 10 Gigabit Fibre-Channel SAN. SPI4.2 eliminates proprietary ASIC-based or specialized network processor interfaces traditionally used to support a broad range of data rates and services. The benefits are a common standards-based interface facilitating inter-connection between diverse devices from multiple manufacturers.
Designed for packet transfer between a MAC device and a network processor or switch fabric, the SPI4.2 interface supports the aggregate bandwidths required of ATM and Packet-over-SONET/SDH (POS) applications. SPI4.2 provides a common interface for 10 Gbps Wide Area Network (WAN), Local Area Network (LAN), Metro Area Network (MAN), and Storage Area Network (SAN) technologies, and it is ideal for systems that aggregate low-data rate channels into a single 10 Gbps uplink for long haul or backbone transmission. Lattice's ORSPI4 FPSC is unique in the programmable market as it embeds the SPI4.2 core in pre-characterized ASIC gates, unlike competitors who ship soft SPI4.2 IP cores which must be integrated into the overall design and face the uncertainties of FPGA place and route timing.
Advantages Over FPGA-Only Approaches
"Unlike other SPI4.2 implementations for FPGAs, the ORSPI4 FPSC embeds all the high-speed functions in an ASIC core of over 1 million gates, allowing the FPGA gates to be used for design-specific bridging functions," commented Stan Kopec, vice president of marketing at Lattice. "Embedding these functions within a hard core assures performance, predictability and interoperability. This implementation also provides a big advantage in terms of total power consumption. Typical programmable-only FPGA IP cores consume upwards of 10W for one SPI4.2 interface implementation. In comparison, the ORSPI4 dissipates less than 2W per SPI4.2 implementation at 900 Mbps operation. This is a big advantage for power hungry 10 Gbps line cards," added Kopec.
"Line cards are getting "smarter" all the time, with the incorporation of NPUs and traffic management capabilities. This intelligence adds to board complexity with the potential for signal skew and strenuous layout constraints," added Kopec. "The SPI4.2 spec defines a de-skew technique that relies on a built-in training sequence with user-selectable repetition rate and duration. Referred to as dynamic alignment, this timing mode eliminates phase errors due to PCB traces of unequal lengths by continuously monitoring the data and adjusting the phase of the clock to align with it. This can be a challenging problem for programmable devices, but our FPSC technology affords us the opportunity to manage dynamic alignment with predictable and reliable ASIC technology," he concluded.
SPI4.2 Core Features
The SPI4 interface blocks in the ORSPI4 FPSC contains these industry-best features:
Multiple SPI4.2 interface cores
| Two independent full-featured OIF-compliant SPI4.2 interfaces for >20 Gbps bandwidth. Supports quarter-rate mode for 2.5 Gbps operation |
| Supports both static and dynamic alignment schemes Supports dynamic bit de-skew over 16 phases of clock Supports receive clock aligned or clock centered transmit data in static mode. |
Parity generation and checking
| DIP-2 and DIP-4 parity generation and checking embedded in ASIC |
| Embedded 1K deep main and shadow calendar built-in, supports scheduling up to 256 ports and hit-less bandwidth provisioning |
User design interface
| User friendly FIFO interface from ASIC to FPGA logic for clock domain transfer and ease of design Support of up to four user clock domains and 32 FIFOs per Tx and Rx |
| Dedicated LVDS drivers and receivers with center tap option increases performance and reduces jitter |
Flow Control flexibility
| An embedded set of write and read port descriptor memories supports a flexible flow control interface for each SPI4.2 port |
| Less than 2W of power for each SPI4.2 interface at 900 Mbps operation with dynamic alignment 1.5W for each SPI4.2 interface at 700 Mbps operation with static alignment |
| Embedded high-speed memory controller for interface to external QDR II SRAM for line-rate packet buffering |
The SPI4.2 cores on the ORSPI4 FPSC provide dual 10 Gbps Physical-to-Link Layer interfaces in conformance to the OIF-SPI4-02.0 specification. Each block provides a bi-directional interface with an aggregate bandwidth of 14.4 Gbps. This is achieved by using 16 LVDS pairs each for transmit and receive channel operating at a data rate of 900 Mbps with a 450 MHz DDR clock. Both static and dynamic alignment are supported at the receive interface. DIP-4 and DIP-2 parity generation and checking are also supported. 8K bytes of data buffering is provided by embedded Dual-Port RAM for both transmit and receive in each SPI-4.2 core. Internal 1K deep main and shadow calendars supports scheduling of up to 256 ports. The Transmit and Receive Status FIFOs can also store flow control information for up to 256 ports, the maximum specified in the SPI-4.2 specification.
In order to provide wire-speed packet processing, the ORSPI4 also contains an independent Memory Controller Block that provides data buffering between the FPGA logic and external memory and supports a throughput of greater than 20 Gbps. Data is transferred to and from memory through two sets of 36-bit unidirectional data lines (one read, one write) operating at up to 200 MHz DDR (400Mbps). A set of 72 data signals is available to transfer data across the core-FPGA interface and allows the system to utilize the bandwidth available with second-generation QDR II SRAMs. Of the 72 data signals, 8 signals can be used either for parity or data. A second memory controller can also be added in the FPGA section to provide two independent line-rate buffers if needed.
High Speed SERDES I/O
The high-speed SERDES block supports four serial links, each operating at up to 3.7 Gbps (2.96 Gbps data rate with 8b/10b encoding and decoding), to provide four full-duplex synchronous interfaces with built-in receiver Clock and Data Recovery (CDR) and transmitter pre-emphasis. The SERDES block is identical to that proven in Lattice's ORT82G5 and ORT42G5 FPSCs, supporting embedded 8b/10b encoding/decoding as well as link state machines for both 10 Gbps Ethernet and Fibre Channel. The state machines are IEEE P802.3ae/D4.01 XAUI compliant and also support FC (ANSI X3.230: 1994) link synchronization. The SERDES in the ORSPI4 FPSC contains industry-best performance with the following features:
Widest range of Programmable Data Rates
| 4 channels with industry-leading performance from 0.6 Gbps to 3.7 Gbps |
Multiple Standards Compliance
| Fibre Channel (1G, 2G), XAUI-Ethernet (10G) and XAUI-FC (10G) |
Rx Jitter Tolerance
| 0.75UI p-p typical, 0.65 UI p-p worst case, exceeds XAUI and Fibre Channel specifications (@ 3.125 Gbps) |
Tx Total Jitter
| 0.17UI p-p typical, 0.24 UI p-p worst case, exceeds XAUI and Fibre Channel specifications (@ 3.125 Gbps) |
Low Power per SERDES Channel
| 225 mW worst case, including I/O buffers @ 3.125 Gbps |
Fast Locking Times
| Bit Realignment 300 nanoseconds (938 bit times @ 3.125 Gbps) nominal |
Transmitter Output (CML)
| Full-amplitude mode: 0.8V p-p Minimum Half-amplitude mode: 0.4V p-p Minimum |
Demonstrated Drive Length
| Over 40 inches (100cm) of FR-4 backplane |
The ORSPI4 FPSC also contains a dedicated microprocessor interface, a 32-bit internal system bus (and 4-bits parity), and built-in system registers that act as the control and status center for the SPI4.2, SERDES, and memory controller blocks. The FPGA portion of the device can also be configured through this interface.
The ORSPI4 FPSC in the 1036 fpSBGA (1mm ball pitch, thermally enhanced fine pitch ball grid array) package is currently shipping. The unit price in quantities of 10,000 is $250.00. The device will also be offered in an 1156 fpBGA (1mm ball pitch, standard plastic fine pitch BGA) package without the SERDES channels. The device is supported by Lattice's ispLEVER® v3.1 design software, a dedicated design kit, and popular third-party synthesis, simulation, and verification tools.
About Lattice Semiconductor
Oregon-based Lattice Semiconductor Corporation designs, develops and markets the broadest range of Field Programmable Gate Arrays (FPGAs), Field Programmable System Chips (FPSCs) and high-performance ISPTM programmable logic devices (PLDs). Lattice offers total solutions for today's system designs by delivering the most innovative programmable silicon products that embody leading-edge system expertise.
Lattice products are sold worldwide through an extensive network of independent sales representatives and distributors, primarily to OEM customers in the fields of communication, computing, computer peripherals, instrumentation, industrial controls and military systems. Company headquarters are located at 5555 NE Moore Court, Hillsboro, Oregon 97124 USA; Telephone 503-268-8000, FAX 503-268-8037. For more information on Lattice Semiconductor Corporation, access our World Wide Web site at http://www.latticesemi.com.
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