Tower Semiconductor standardizes on TriCN's interface IP

Newly Established Technology Partnership Includes TriCN’s Base I/O Library, High-Performance I/Os For Tower’s 0.18 micron Process

SAN FRANCISCO, CA – December 8, 2003--TriCN, a leading developer of intellectual property (IP) for high-speed semiconductor interface technology, and Tower Semiconductor (NASDAQ: TSEM; TASE: TSEM), a premier IC wafer-manufacturing foundry, today announced an agreement under which TriCN will provide its Base I/O library and a suite of high-performance interface IP to Tower for use in their 0.18um process.  Tower will make this IP available to customers designing high-performance chips for production at Tower’s Fab 2 facility.

TriCN’s Base I/O library is a comprehensive set of cells containing all elements required to produce a pad ring, allowing developers to create the interface foundation for their IC designs.  The Base I/O library is specifically geared to support designers developing high-speed applications.  Additionally, the company’s Interface Specific I/Os (ISI/Os) are tuned toward particular high-performance interface applications such as memory, networking and graphics.  As a result customers will save valuable time-to-market while significantly mitigating their development risk. 

“We’re standardizing on TriCN technology for our interface IP needs because of their distinguished track record developing high-performance interfaces,” said Sergio Kusevitzky, V.P. of IP and Design Services with Tower Semiconductor.  “Furthermore, the flexibility of their Base I/O library allows customers with a wide range of design applications to successfully develop chips with minimal risk. We believe this is a key benefit for customers designing next-generation ICs for production in our fab.”

“Tower Semiconductor’s reputation as a well-established provider of quality foundry services aligns directly with our corporate philosophy of ‘getting it right the first time,’” said Joe Curry, CEO with TriCN.   “The power-up success rate for chip designs using our interface IP is unmatched in the industry, and we look forward to many successful engagements with Tower customers.”

About TriCN’s Base I/O Library
The TriCN Base I/O Library provides semiconductor designers with a foundation for developing a complete pad ring assembly for their chips that eliminates numerous technical complexities.  TriCN’s library differentiates itself from competing products with the variety of cells offered, as well as the performance and flexibility of those cells.  Along with the standard array of Corners, Breakers, Power and Ground, and LVTTL/LVCMOS cells, TriCN’s Base I/O Library includes higher performance HSTL, SSTL-2, PCI 2.2, PCI-X, and USB 1.1 cells currently lacking in most competitive offerings.

A key feature of TriCN’s Base I/O library is that power and ground cells have been developed to provide more current than competitive products, allowing designers to achieve an effective area savings.  Additionally, all TriCN Base I/O cells have built-in noise isolation features that provide improved operation and reliability in higher-performance applications.  Finally, TriCN’s Base I/O cells can be used in either a Flip-Chip or Bond-wire package application, providing significant flexibility to semiconductor designers.

ISI/O: Interface Specific I/O Solutions
TriCN has created a family of validated and complete ISI/Os that are tailored to specific interface applications.  Based on generic, broadly applicable interface standards (such as HSTL, SSTL, LVDS), these products have been developed to account for the complete range of environmental constraints at the chip and system level.  This enables seamless integration into chip development, and allows customers to achieve high performance targets, while reducing time-to-market.  Moreover, this pre-validation of the design significantly reduces risk for IC developers.  In particular, TriCN’s ISI/Os are targeted toward communications, memory and graphics applications, and include products such as DDRII-SDRAM, GDDRII, QDR-SRAM, DDR-FCRAM II, SPI-4.2, and HyperTransport.

About Tower Semiconductor, Ltd.
Tower Semiconductor Ltd. is a pure-play independent wafer foundry established in 1993. The company manufactures integrated circuits with geometries ranging from 1.0 to 0.18 microns; it also provides complementary manufacturing services and design support. In addition to digital CMOS process technology, Tower offers advanced non-volatile memory solutions, mixed-signal and CMOS image-sensor technologies. To provide world-class customer service, the company maintains two manufacturing facilities: Fab 1 has process technologies from 1.0 to 0.35 microns and can produce up to 16,000 150mm wafers per month. Fab 2 features 0.18-micron and below process technologies, including foundry-standard technology, and will offer full production capacity of 33,000 200mm wafers per month.
The Tower Web site is located at www.towersemi.com.

About TriCN
Founded in 1997, San Francisco, California-based TriCN is a leading developer of high- performance semiconductor interface intellectual property (IP). The company provides a complete portfolio of IP for maximizing data throughput on and off the chip, ranging from a Base I/O library to multi-gigabit SerDes products. This IP is designed for IC developers addressing bandwidth-intensive applications in the communications, networking, data storage, and memory space. TriCN's customers range from startup to established fabless semiconductor and systems companies, including Philips, General Dynamics, SGI, IBM, Cognigine, Internet Machines, and Apple Computer.

For more information, please visit TriCN’s web site at www.tricn.com.

TriCN: The Single Source for Interface IP™