The first solution on the market to combine the flexibility of FPGA with the efficiency of ASICs
CUPERTINO, CALIFORNIA — January 26th, 2004 — Leopard Logic, Inc. today introduced Gladiator™ CLD™, a family of configurable logic devices featuring an innovative new architecture that combines ASIC and FPGA technologies into the industry’s first 100% configurable implementation platform for system designers. Customers can perform instant design changes as with FPGAs, while leveraging the more efficient ASIC logic for the fixed blocks of their design. The result is a solution that defines a new standard for high-performance, low-power and fast turnaround time at industry leading price points.
The Gladiator CLD family consists of multiple devices with capacities ranging up to 25M system gates and up to 10Mb of on-chip memory. Not limited by pre-defined functionality, Gladiator becomes a customer or market segment specific device by implementing substantial amounts of high-speed logic in the mask-programmable (MP) section of the device. Further customization is achieved by programming the field-programmable (FP) fabric, which allows for an unlimited number of reconfigurations by simply downloading a new bitstream into the device, thus offering optimal in-field upgradeability. The HyperBlox™ MP and FP fabrics share a unified core cell architecture, allowing for simple partitioning and full automation by Leopard Logic’s design flow. Gladiator’s elimination of vendor-driven back end processing, its single-layer technology for minimum non-recurring engineering (NRE) costs, and its in-field-programmability for risk mitigation make it the device of choice for today’s high performance access/edge networking, SAN and wireless infrastructure markets.
“Customers are often caught between a rock and a hard place where ASICs are not an option because of long lead times, high risk and the lack of flexibility, while FPGAs can’t meet critical performance or power requirements. By combining the flexibility of FPGAs with the efficiency of ASICs, Gladiator is the ideal choice for customers caught in the gap. With system speeds of 500MHz, high-performance memories and I/Os, and extreme DSP performance in a single-chip, Gladiator is addressing today’s most pressing market needs. In addition, our customers benefit from a turnaround time that produces an unprecedented acceleration in time to revenue,” said Chris Phillips, president & CEO of Leopard Logic.
Today, the only way to achieve high integration and performance while providing flexibility on the system level is to combine ASICs and discrete FPGAs on a printed circuit board. However, this approach limits system performance and introduces other issues such as high power consumption, large board space and high costs. Inevitably, applications become limited by the rigid partitioning and bandwidth bottleneck between the devices at the board level.
By integrating the FPGA fabric on the same chip, Gladiator CLD delivers significantly increased performance, while simultaneously lowering power consumption. With a design cycle and upfront investment comparable to an FPGA, Gladiator offers the lowest total cost of ownership for production volumes ranging from 1k-100k units.
The market for devices using embedded FPGA technology is forecast to skyrocket to over $650M in 2007 at a CAGR of 115% according to market research firm In-Stat/MDR. “ASICs just don’t work for many companies anymore because of escalating costs and extending development cycles. The FPGA market is profiting from this trend. Over the next several years we see a fast growing market for hybrid devices that use a combination of hardwired logic and embedded FPGA fabrics,” states Jerry Worchel, Senior Analyst at In-Stat/MDR.
Leopard Logic’s patented technology features the industry’s first fully hierarchical, directly buffered, point-to-point interconnect, which is at the root of Gladiator’s superior speed, utilization, predictability and reliability. The SRAM based HyperBlox FP fabric can be reprogrammed by the user anytime. The HyperBlox MP fabric uses the identical logic core cell architecture, but replaces the SRAM configuration with a single-layer mask configuration to achieve significantly higher density, increased performance and lower power consumption.
The HyperBlox FP and MP fabrics are combined with optimized memories, multiply-accumulate (MAC) units and flexible high-speed I/Os to realize a fully customer configured design. Leopard Logic’s unified design environment allows rapid timing closure at the designer’s desktop without tedious design iterations or exposure to back end, silicon deep sub-micron (DSM) issues.
The first member of the Gladiator CLD device family is the CLD6400, which provides 6.4M system gates, 2.3Mb of on-chip memory and 680 I/Os. Operating at system speeds of 500MHz, the CLD6400 offers a 32 GMAC/second DSP capability, has 16 on-chip PLLs and DLLs to drive global clocks and implement high-speed interfaces, and a maximum power consumption of 5 Watts. The CLD6400 is manufactured in TSMC’s 0.13 CMOS process on 300mm wafers to deliver high performance and reliability combined with low cost.
Using the ToolBlox™ suite of development tools and design kits, customers implement and validate their designs just like FPGAs. This process produces the bitmap information for the MP fabric and a bitstream to program the FP fabric. The bitmap is then sent to Leopard Logic, who delivers samples to the customer in 4 weeks or less. The bitstreams can be loaded into the CLD device through JTAG or a serial PROM interface. The device test is transparent to the customer using built-in self-test (BIST) and full scan circuitry. Once the design has been validated in the system, customers can ramp into volume production within weeks.
The Design Flow
Unlike Structured ASICs, which are not field-programmable and require back end processing by the vendor, Gladiator devices incorporate an FPGA-like design flow that eliminates the potentially lengthy timing closure cycles associated with cell-based ASICs, gate arrays and structured ASICs. The tight integration of Leopard Logic’s ToolBlox suite with leading industry standard design tools, allows customers to utilize existing infrastructure and proven design methodologies, in order to achieve immediate user productivity.
A Complete Solution
To ensure the fast and successful implementation of Gladiator CLD devices, Leopard Logic customers have access to best-in-class third-party intellectual property (IP) cores, pre-qualified for seamless integration into Gladiator devices. Founding members of the Gladiator IP alliance are Amphion Semiconductor, Eureka Technology, Mentor Graphics and Modelware.
“We are extremely pleased with the positive feedback we received from customers and partners about Gladiator CLD. The high performance, inherent IP protection and fast time to money make it the ideal delivery platform for advanced IP solutions. The strong support from our IP and channel partners enables us to provide a great selection of proven IP for our target markets and world-class customer support to allow for the quick adoption of Gladiator CLD devices,” commented Stefan Tamme, Leopard Logic’s vice president of sales and marketing.
Pricing and Availability
The CLD6400 is available now and pricing will be $99 in 100k unit volumes in early 2005.
About Leopard Logic, Inc.
Leopard Logic is a fabless semiconductor company headquartered in Cupertino, California. Leopard Logic provides Gladiator CLD, a family of configurable logic devices that combine ASIC and FPGA technologies in a single device. This innovative combination increases performance, reduces power consumption and board space, and minimizes costs when compared to discrete FPGA and ASIC implementations. The devices can be used across a wide range of markets and applications that require flexible logic solutions, such as networking, storage and wireless. For more information visit our website at http://www.leopardlogic.com.
Leopard Logic, the Leopard Logic logo, Gladiator, CLD, HyperBlox, HyperRoute, HyperVia and ToolBlox are trademarks of Leopard Logic, Inc. All other company and/or product names are the trademarks and/or registered trademarks of their respective owners.