SAN MATEO, Calif. Aptix Corp. has updated the logical mapping software for its System Explorer emulation system, shrinking the time it takes for users to get a design programmed into the emulator.
Synthesis streamlining and debug improvements to the Design Pilot tool have combined to shrink time-to-emulation from weeks to days, said Raj Mathur, design pilot product manager at Aptix (San Jose, Calif.).
"Heretofore, mapping from [register transfer level] to our box has been an endeavor for our customers," said Mathur. "With this release, we concentrated on improving time-to-emulation through ease of mapping at the register transfer or gate levels."
The previous version of the technology had been tentatively called Expedition, but Aptix was required to change the name for trademark reasons.
Priced at $100,000, the tool lets users create prototypes for systems-on-chip (SoCs) from the register transfer level, directing Synopsys' FPGA Compiler II to compile code for compilations for Aptix's emulation system. Users must license a copy of FPGA Compiler II from Synopsys. That tool starts at $8,000.
FPGA programming bypass
"Design Pilot is mainly targeted at ASIC and SoC designers who don't know or don't want to know the intricacies of programming the FPGAs on our System Explorer emulator," said Mathur. The tool essentially automates the front-end logic mapping and feeds the $85,000 Explorer place and route FPGA and field-programmable circuit board (FPCB) software. Users can use third-party software from other EDA vendors or FPGA vendors to do logic design, Mathur said, but such users would likely lose the time-to-emulation advantage offered by Design Pilot.
Mathur said the single biggest addition to the revised tool is an engine that forces FPGA Compiler II to perform bottom-up synthesis. According to Mathur, Synopsys created FPGA Compiler II to get complete designs on FPGAs, not to partition large ASICs and SoC desig ns onto several FPGAs for emulation. But the new version of Design Pilot reads the logical hierarchy from an ASIC or SoC design and then feeds FPGA Compiler II digestible blocks. Design Pilot then plots in a netlist that is compliant with the original logical hierarchy.
Mathur said the previous version of the tool also required two iterations through synthesis. "But now we have added our own code to Design Pilot so it only requires one call to FPGA Compiler II," said Mathur.
Design Pilot includes improved scripting for running the tool in an incremental mode. It also supports Synopsys Presto Compiler, a revamped compilation engine within Synopsys' FPGA Compiler II that replaces VHDL and HDL compilers and runs Verilog 2000.