This new version of Magillem (R) offers the capability to specify and verify a system both at transactional and RTL levelsCergy, France - February 2, 2004
- Prosilog SA, the leading provider of innovative solutions for SoC design and verification, announce the availability of the release 2.0 of its Magillem (R) tool, the graphical generator of SoC platform. Magillem (R) allows an easy interconnection between different IP's with the AMBA, CoreConnect, VCI and OCP protocols.
The IP Creator module generates an OCP or VCI wrapper which facilitates the interconnect of the IP to the targeted bus. The code generated for the complete system is VHDL, Verilog or SystemC. Moreover, as a native XML-based platform, Magillem (R) is following the recommendations from the SPIRIT consortium.
The Magillem (R) 2.0 release is particularly important for System designers who want to build a complete transactional platform in SystemC at different levels of abstraction, and mix HDL and SystemC IP's. The verification challenges are also addressed with the availability of the eVC (e Virtual Component) OCP2.0 module. New features of Magillem (R) 2.0 Release
- Support of SystemC transactional levels (PV, PVT, CC).
- TL2-TL1 & TL1-TL0 adapters for OCP 2.0.
- IP Creator OCP 2.0.
- Prosilog's OCP 2.0 eVC.
- Import of VHDL, RTL and TLM SystemC IPs in XML format.
- SystemC AMBA CLI bus model library.
- SystemC AMBA CLI CC-RTL adapters.
Prosilog is continuously developing its Magillem (R) tools suite in order to propose to its customers innovative solutions for cutting significantly their design cycle time. Magillem and Nepsys are registered trademarks of Prosilog SA.
All other trademarks are the property of their respective holders.