Electronic System-Level Design a Significant Focus of European Design Automation ConferenceSAN JOSE, Calif., February 10, 2004
- CoWare Inc., the leading supplier of system-level electronic design automation (EDA) software and services, will showcase its complete solution for electronic system level (ESL) design—including tools for creation of embedded processors, on-chip buses, and DSP algorithms; architecture of optimized SoC platforms; and hardware/software co-design—during the Design Automation and Test in Europe (DATE) conference, to be held in Paris, France, February 16-20, 2004 (www.date-conference.com
). CoWare will take part in several panels and presentations focused on ESL design, and will offer demonstrations of its entire product line.
Customers can visit CoWare’s booth, number 6100, for demonstrations of the CoWare products, including the ConvergenSC™ system level design solution—featuring the industry’s fastest SystemC simulator for IP and platforms; SPW, with its growing set of libraries including recently announced UWB support; and the latest release of the LISATek suite of tools for embedded processor modeling, design, and software tool generation. In addition, customers can see the integration between the CoWare ConvergenSC and Cadence Incisive products—a result of the close alliance between the companies. Demonstrations of the recently announced PowerEscape™ power optimization products—of which CoWare is a global OEM—will also be available.
While in the CoWare booth, customers can learn more about a new book available from Kluwer Academic Publishers, entitled Design of Energy-Efficient Application-Specific Instruction Set Processors. The book is co-authored by Tilman Glökler of IBM Deutschland Entwicklung GmbH, Böblingen, Germany; and Heinrich Meyr of Aachen University of Technology, Germany. Dr. Meyr is chief scientist for CoWare.
On Tuesday, February 17th, Alan Naumann, president and CEO of CoWare, will take part in a panel discussion on “Advanced Solutions for SoC Design,” and CoWare will present on “Generating TLM Bus Models from Formal Protocol Specifications” during the European SystemC Users Group Meeting (ESCUG).
On Wednesday, February 18, CoWare will participate in a panel on abstract modeling, as well as a seminar in the Cadence Design Systems booth, number 9300, called “Cadence & CoWare Simulation Environment.”
On Thursday, February 19th, Mark Milligan, vice president of marketing, will take part in a panel entitled “Why Has System-Level Design Taken so Long to Gain Momentum?” and CoWare will present on transaction-level modeling (TLM) during the Doulos Design Workshop.
In addition to these panel presentations, CoWare will present three technical papers during the conference. For more information, including dates and times of CoWare’s activities at DATE, visit www.CoWare.com and click on the DATE logo.About CoWare
CoWare is the leading supplier of system-level electronic design automation (EDA) software tools and services. CoWare offers a comprehensive set of electronic system-level (ESL) tools that enable SoC developers to “differentiate by design” through the creation of system-IP including embedded processors, on-chip buses, and DSP algorithms; the architecture of optimized SoC platforms; and hardware/software co-design. The company’s solutions are based on open industry standards including SystemC. CoWare’s customers are major systems, semiconductor, and IP companies in the market where consumer electronics, computing, and communications converge.
CoWare’s corporate investors include ARM Ltd. [(LSE:ARM);(Nasdaq: ARMHY)], Cadence Design Systems (NYSE:CDN), STMicroelectronics (NYSE:STM), and Sony Corporation (NYSE:SNE). CoWare is headquartered in San Jose, Calif., and has offices around the world. For more information about CoWare and its products and services, visit http://www.coware.com
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