FPGAs add fixed cores for communications drive

FPGAs add fixed cores for communications drive
By Jerry Ascierto and Will Wade, EE Times
May 15, 2001 (1:29 p.m. EST)
URL: http://www.eetimes.com/story/OEG20010514S0084

SUNNYVALE, Calif. — Three major FPGA vendors are using fixed cores to implement communications standards in new product lines, in moves that underscore both the importance of the communications market to this semiconductor sector and a push toward specialization in programmable logic.

The trend signals a dramatic shift from the original FPGA model of providing vanilla programmable chips sold to all comers.

Actel Corp. has introduced a suite of chips that puts physical-layer (PHY) interfaces for several communications standards alongside a large block of programmable gates. Xilinx Inc. is taking a similar but smaller step, rolling a soft core with the RapidIO format, the first PHY solution available to date supporting that standard.

Altera Corp. said it is developing separate intellectual-property (IP) cores to support the HyperTransport and RapidIO interconnect architectures. And Xilinx is expected to follow with its own core for Hype rTransport, an interface developed by Advanced Micro Devices Inc. that's fast gaining ground in networking.

"Over the next several years, we are going to see some major changes in the products that come out of the FPGA suppliers," said Dennis Kish, corporate vice president of marketing at Actel. "It's time for this market segment to mature and to fragment."

FPGA gate counts are rising toward the 5 million mark, but users don't always want all those gates, said Bill McClean, president of market research firm IC Insights Inc. (Scottsdale, Ariz.). Using them to design every function from scratch is "not as efficient as simply plopping in a fixed core."

In large part, the fragmentation in FPGAs is an outgrowth of a fragmentation in communications markets, which are swamped by what Justin Cowling, senior manager of Altera's IP business division, calls "the explosion in interfaces.

"The network processor vendors like Broadcom are very much adopting HyperTransport as an interface for the data path, but RapidIO tends to be more packed in the control plane," said Cowling.

"What's interesting is that you find HyperTransport supported by an OEM or a couple of ASSP [application-specific standard product] vendors, but not by all the chips in a particular system. So we're asked to do a lot of bridging support between some of these interface technologies to other communications interfaces. This is where PLD comes in."

Altera has quietly begun developing fixed HyperTransport and RapidIO physical-layer cores. "All of our customers want to take advantage of the latest devices with high-speed interfaces, but nobody knows which will survive," Cowling said.

"We recognize what's happening, this fragmentation, and we really kept that in mind when we designed the Apex-II architecture," he said. "It's specifically an I/O-rich family, and probably the top priority of that family is to port both RapidIO and HyperTransport in an inexpensive manner."

Suitable for end use

Actel's Kish said t hat FPGAs are fast shedding their prototype-only past. Thanks to finer process geometries and better architectures, today's FPGAs are smaller and faster than earlier generations of programmable parts, at a time when product life cycles for many end systems have shortened. Just as system designers find they no longer have time to wait for an ASIC, Kish said the FPGA vendors are showing up with programmable parts suitable for end-use applications.

With the FPGA vendors looking at specific target markets, Actel president and chief executive officer John East said they will need specific designs aimed at each application, just like chip companies that produce standard products. "We are trying to define some new niches for the FPGA space," East said.

The first such niche for Actel is in communications bridges, devices within systems that can span the gap between different bus or networking formats, or between two incompatible chips using the same format. Called the BridgeFPGA family, the chips will have both analog PHY components and fixed digital protocol controllers, for both serial and parallel communications formats such as Infiniband, Universal Serial Bus and RapidIO.

Core need

The bulk of each chip, perhaps 85 to 90 percent, will remain a large programmable block, allowing users to design their own functionality. However, East said that with so many formats now in use, the basic function of bridging the gap between two devices that need to talk to one another is becoming a core need for many potential customers.

The BridgeFPGA architecture will allow Actel to use just three versions of mask sets to create dozens of different designs linking separate communications formats. Doing all of these in standard products would be prohibitively expensive, East said.

Other players in the FPGA space are treading the same path. Xilinx will announce this week at the Applied Computing Conference an FPGA core for the Rapid IO interconnect standard. The first commercially available PHY sol ution within the RapidIO infrastructure, the Real RapidIO core complies with the 1.1 revision of the specification, released in March.

RapidIO's fast industry uptake can be attributed to its evolutionary approach, which squeezes more life out of the aging, and ubiquitous, PCI bus, said Babak Hedayati, director of business development for Xilinx's IP solutions division. "RapidIO is based on low-voltage differential-signaling technology, which all FPGAs and most silicon support. One of the greatest selling points of RapidIO is that it works with legacy software," he said.

Actel's East concurred, noting that the BridgeFPGA parts also leverage the fact that almost all serial-connection protocols use LVDS. Thus, the PHY components for each format have some fundamental similarities. Actel has struck a licensing deal with Tality Corp. (San Jose, Calif.), which will provide the FPGA company with access to all of its protocol intellectual property.

The Real RapidIO core, optimized for Xilinx's high-end Virtex-II family, offers performance levels up to 8 Gbits/second per port, resulting in an aggregate bandwidth of hundreds of gigabits per second. Xilinx worked with spec author Motorola Inc. on the core, which was fully verified using version 1.4 bus-functional models provided by the RapidIO Trade Association.

RapidIO and HyperTransport are often seen as competing specifications, each designed to coax more bandwidth out of the PCI bus. "Right now, everybody's trying to figure out which will be the next PCI bus," said Hedayati.

Whereas the PC-flavored HyperTransport has seen broad adoption in the networking industry, the embedded community has favored RapidIO, which was designed with a focus on embedded applications. Both Xilinx and Altera support HyperTransport in their high-end lines, and are likely to introduce HyperTransport cores in the coming months.

Hedayati noted that FPGA vendors have begun getting customer requests to support the various communications standards. The programmable chi ps have always been capable of modification to do anything a customer wanted, but the process took time. Adding fixed cores saves time, but only makes sense if there is a strong demand from a specific customer base, he said.

Interface overload

"We find ourselves in the middle of all of these various proposed interfaces," said Hedayati. "A lot of our customers actually want many of these, or different organizations in the same customer base may want different things. We think that over time, certain applications will prove that they need certain kinds of interfaces, and that will be the deciding factor."

Tom Cox, a chairman on the RapidIO board and director of strategic planning at Tundra Semiconductor Corp. (Ottawa), said that in addition to FPGA vendors, ASIC heavyweights like LSI Logic Corp. are currently ramping up RapidIO product.

"Since it's based on LVDS, you don't need to have the leading-edge interfaces of circuits to make [RapidIO] work," Cox said. "It's economical, it's got a small footprint that's appealing to the FPGA vendors.

"The FPGA guys can't play Infiniband just yet," he added, referring to the server interface standard just ramping up. "They'll get there, it's just too complex right now."

Xilinx conservatively estimates that systems using RapidIO will begin to hit the streets in roughly 18 to 24 months. The company's 8-bit-port RapidIO PHY, optimized for Virtex-II devices, is available now, priced at $17,995. The soft core can be purchased as a Xilinx LogiCore product through the Xilinx IP Center.

The Actel BridgeFPGA parts will hit the market later this quarter, but East said he doesn't expect to ship any significant volumes for about a year.

For its part, Altera said that its Apex-II line was specifically designed to address these coming communications interface needs. "With Apex-II we recognized that effectively, customers are looking for richer features, so we put two banks on there, dedicated I/O circuitry, that support both RapidIO and Hyp erTransport," said Cowling. "There are so many different requirements from an IP perspective, but we're currently developing IP for them all."

Altera's Apex-II line, which is scheduled to ship in July, features a "True-LVDS" solution at up to 1 Gbit/s and a "Flexible-LVDS" solution at up to 624 Mbits/s. All densities in the line include 36 input and 36 output True-LVDS channels, which are then subdivided into four banks. The banks have independent clock domains capable of operating at different frequencies. On the Flexible-LVDS side, users can choose from 56 or 88 I/O channels, depending on the device.

Split support

Peter Woo, a senior product marketing manager for Altera, said that in terms of volume, Altera has seen pretty much a split down the middle from customers looking to support RapidIO and HyperTransport. "We're happy if any one of them takes off like gangbusters," he said. "But in the meantime, we'll support [both] of them."

Analyst McClean said that most FPGA vendors will attempt to focus on specific target markets, devising fixed cores to create a value-add that makes them more attractive to a particular user group. "This trend toward increasing specialization will continue for quite a while," he predicted.

Actel's East said that the entire FPGA market is going through this process of segmentation, with each company attempting to find its own specialty. Since almost all of the vendors make at least half of their sales in communications applications, it is no surprise that this seems to be the first area of specialization.

"The way to make money in this market is to be the first to define a new niche and to get there first," East said.