Eastleigh UK, February 20, 2004 - TransEDA, a leader in coverage and ready-to-use verification solutions for electronic designs, today announced several unique solutions based on the synergy of TransEDA’s advanced Coverage Products and TNI-Valiosys’ innovative Formal Verification Technologies.
In a move that confirms the objectives of the merger undertaken in September 2003, TransEDA has chosen the DATE Conference in Paris to present several coverage and verification solutions that leverage technologies previously developed by both companies. TransEDA introduced a suite of tools that address the verification bottlenecks in SoC design from specification to sign-off by focusing not only on evaluating the coverage, but also on guiding designers to detect and correct the logic areas that need improvement, as well as to optimize their assertions and simulation vectors.
"We merged the companies in order to leverage our complementary technologies", said Jean-Luc Bouvresse, C.E.O. of TransEDA. "Our vision is to bring new dimensions in coverage to our customers, solutions that offer unique value by enabling our customers to go beyond traditional code coverage analysis and use a coverage-driven methodology to reduce the time they spend in design verification."
TransEDA finished the fourth calendar quarter and its first full quarter after the merger with increased sales volumes, returning the company to profitability for the first time since June of 2002. Customers showed their confidence in the new company by renewing their commitments with TransEDA, for new products and maintenance.
"Our applications support and sales people found it easy to explain the value of the merger to customers and to show them how our joint products will help them meet their design and verification objectives now and in the future", adds Modesto Casas, responsible for Worldwide Sales and Marketing at TransEDA, "Customers are validating our vision by increasing their investment in our products and services."
TransEDA’s New Dimensions in Coverage presented at DATE 2004
Bus protocol coverage tools that automatically verify coverage and compliance with a standard bus specification protocol, by creating the design properties and the environment, by applying formal verification to check functional compliance and by verifying the system performance and linking results to protocol specification.
Coverability improvement tools that guide the designer to full coverage, by applying formal techniques to identify problem areas and by automatically creating assertions and optimizing vector suites to achieve better coverage.
Emulation coverage tools that expand quality metrics to all phases of the design, by enabling the migration of coverage based verification from simulator to emulator, by measuring coverage on emulated hardware and by dramatically reducing the time required to get coverage information on large designs.
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