Training firm offers free Vera TCP/IP packet generator with a built-in functional coverage tracker
![]() ![]() | |
EE Times: Latest News Training firm offers free verification IP | |
Richard Goering (02/26/2004 7:00 PM EST) URL: http://www.eetimes.com/showArticle.jhtml?articleID=18200879 | |
SANTA CRUZ, Calif. As a way of spreading the word about its classes and workshops, Si-Concepts is offering a free Vera TCP/IP packet generator with a built-in functional coverage tracker. The company is also offering a tutorial on coverage-driven testbenches at the DVCon conference March 1, 2004. Si-Concepts is a "design knowledge company," said Shahid Khan, president. In addition to the upcoming four-hour tutorial at DVCon, the company offers a three-day workshop, created for Synopsys, entitled "VERA II: Testbenches and Test Cases For Complex Designs." The Vera TCP/IP packet generator is available for download from Si-Concept's web site. Khan said the company is offering free verification intellectual property (IP) because they want people to register for the DVCon tutorial or the Vera II workshop. "I think people learn best looking at an example from a practical environment," he added. The packet generator produces TCP/IP packets with random payloads, and provides randomization control for header fields of a TCP/IP packet. Fields such as IP source address, IP destination address, TCP source, and destination port numbers are settable by user-specified constraints. Calculated fields such as header checksum and TCP checksum are computed correctly after randomization has occurred, Khan said. The built-in coverage tracking and reporting lets users visualize the effectiveness of their randomization constraints by generating statistical reports on the generated packets. "For anybody who has the TCP/IP protocol, this will generate packets that can be entered into the RTL environment," Khan said. "This is functional coverage, not line coverage. Based on how the RTL interacts with these packets, you can see if any areas are not covered from a functionality standpoint." The packet generator does not require a license, or attendance at one of the company's workshops.
|
Related News
- Agnisys Offers Free Register Generator for UVM
- TPACK Introduces SOFTSILICON a Standard Chip with Built-in flexibility Ideal for Packet Transport Applications
- LogicVision Announces Production Release of Memory Built-In Self-Repair and ScanBurst At-Speed Scan Solution Integrated With Mentor Graphic's FastScan and TestKompress
- Xilinx Delivers Virtex-5 LXT FPGAs With Industry's First Built-In PCI Express Block And Low-Power Serial I/O
- Atmel Introduces a Re-programmable Rad-hard FPGA with Built-in Single Event Upset (SEU) Protection for Space Applications
Breaking News
- RISC-V International Promotes Andrea Gallo to CEO
- See the 2025 Best Edge AI Processor IP at the Embedded Vision Summit
- Andes Technology Showcases RISC-V AI Leadership at RISC-V Summit Europe 2025
- RISC-V Royalty-Driven Revenue to Exceed License Revenue by 2027
- Keysom Unveils Keysom Core Explorer V1.0
Most Popular
- RISC-V Royalty-Driven Revenue to Exceed License Revenue by 2027
- SiFive and Kinara Partner to Offer Bare Metal Access to RISC-V Vector Processors
- Imagination Announces E-Series: A New Era of On-Device AI and Graphics
- Siemens to accelerate customer time to market with advanced silicon IP through new Alphawave Semi partnership
- Cadence Unveils Millennium M2000 Supercomputer with NVIDIA Blackwell Systems to Transform AI-Driven Silicon, Systems and Drug Design
![]() |
E-mail This Article | ![]() |
![]() |
Printer-Friendly Page |