Is that an LUT in my CPLD?
San Jose,Calif., March 8, 2004—For nearly 15 years, Altera (NASDAQ: ALTR) has held the number one position in the complex programmable logic device (CPLD) market. With over 10,000 CPLD users annually, more than 350 million units shipped worldwide, and $4 billion in cumulative sales, the MAX® brand has been synonymous with CPLDs since the introduction of Altera's MAX 5000 family in 1988. Today, Altera reinforces its leadership and sets a new standard for the industry with the launch of the MAX II family, employing a radical new version of the CPLD architecture. In stark contrast to traditional CPLDs, MAX II devices are built on a 0.18-micron embedded flash process based on a look-up table (LUT) architecture. As a result, the new family is half the cost, one-tenth the power, four times the density, and twice the performance of its predecessor. (For more details about MAX II features, see the related press release, or log on to www.altera.com/max2.)
"Our customers are in search of an alternative to small and inflexible ASICs and ASSPs," said Erik Cleage, Altera's senior vice president of marketing. "This presents a giant opportunity to further the value proposition of CPLDs. Based on discussions with our customers, we decided the time was right to buck tradition and to do something dramatic to bring compelling, new benefits to the table."
A New Twist to a Classic Tale
As a result of direct input from more than 500 customers around the globe, Altera set aggressive goals for the new MAX II family. "Some of their expectations were obvious: the new chip had to be faster, smaller, lower cost, less power hungry, and much higher in density," said Cleage. "What was not obvious was how to derive significant improvements from 15-year old CPLD technology; the macrocell architecture is not scalable beyond .22-micron," he said.
To meet the basic needs of CPLD users today and to deliver the expanded CPLD feature set they required, Altera utilized a non-volatile, embedded flash process and adapted the LUT architecture from its highly successful FPGA families. As a result, the new devices deliver twice the performance and quadruple the density at a tenth of the power consumption of previous MAX generations. In addition, die sizes are one quarter the size of the smallest competing CPLDs. Software support for the MAX II family is now included in the powerful Quartus® II design tool. Experienced MAX users will find the same, familiar user interface as MAX+PLUS® II software, but will now have access to a broader range of silicon solutions–from CPLDs to FPGAs–all within the same environment.
"As with our recently launched Stratix™ II FPGAs, we've taken the same approach with MAX II CPLDs," continued Cleage. "We assessed the market opportunity, set some aggressive goals, and completely overhauled the architecture to achieve them. We are staying true to our legacy of innovation in the programmable logic industry."
Altera Corporation (NASDAQ: ALTR) is the world's pioneer in system-on-a-programmable-chip (SOPC) solutions. Combining programmable logic technology with software tools, intellectual property, and technical services, Altera provides high-value programmable solutions to approximately 14,000 customers worldwide. More information is available at www.altera.com.