Improv Systems's Jazz DSPs linked to ARM; Hynix taps Virtual Silicon
Jazz DSPs linked to ARM; Hynix taps Virtual Silicon
By Michael Santarini, EE Times
May 7, 2001 (10:16 a.m. EST)
URL: http://www.eetimes.com/story/OEG20010507S0010
Improv Systems Inc. and ARM Ltd. have released a system-on-chip development environment for mixing Improv DSPs with ARM's embedded RISC processors. The Jazz Rehearsal product consists of a development board that implements Improv's configurable methodology and its Jazz DSP cores, and interfaces directly with the ARM Integrator board, said Cary Ussery, founder, president and chief executive officer of Improv (Beverly, Mass.). "Jazz Rehearsal allows designers to model the integration of ARM's RISC microprocessor cores with a Jazz-based SoC [system-on-chip]," said Ussery. The goal is "to demonstrate ARM processors working with Jazz DSPs for the networking market."
Rehearsal uses an FPGA implementation of up to three Jazz processors, each situated on an individual, stackable card. The board links with the ARM Integrator/AP platform through the Cambridge, England, company's high-performance Amba bus interface, allowing designers to develop and test applications based on a combination of the two companies' technologies. This solution incorporates ARM's two recently announced Amba configurations for the SoC system architecture: the Multi-layer Advanced High-performance Bus (AHB) and AHB-Lite.
Improv has a similar offering linking a Jazz-based board to MIPS development boards. Ussery said the environment is integrated with Improv's development tool suite, which features a Java-based application development and debug environment, an advanced compiler, a graphical environment for customizing the Jazz processor and a cycle-accurate instruction-set simulator.
The first public demonstration of the ARM version of Jazz Rehearsal will be an implementation of Improv's voice-over-packet integrated access device SoC at the Networld+Interop show in Las Vegas this week. The demo can be viewed at both the ARM booth (No. 8838) and the Improv booth (No. 8644). The Jazz Rehearsal Card for the ARM Integrator ASIC Platform is available now for $7,500. Delive ry lead time is four to eight weeks. See www.improvsys.com.
---
Virtual Silicon Technology Inc. and Hynix Semiconductor Inc. (formerly Hyundai Electronics) will jointly develop and market products using Virtual Silicon's advanced nonvolatile memory libraries, eSi-NVM. The companies said Hynix will initially deploy the technology in its high-performance embedded products starting next year.
The pairing will allow system-on-chip designers to embed E2PROM or flash in Hynix Semiconductor's baseline 0.25-micron CMOS logic processes. Virtual Silicon claims the eSi-NVM cells are a low-cost and low-power embedded-memory solution for many market segments, such as wireless communications, portable computing, consumer electronics and industrial automation.
Hynix plans to use this technology for its internally developed products slated for rollout in the first quarter of 2002, and will also make it available to its foundry customers. Virtual Sili con cites the small size the eSi-NVM cell as its selling point over E2PROM technology, claiming the eSi-NVM cell size is more than 40 percent smaller. For details, visit www.virtual-silicon.com or www.hynix.com.
Related News
- Arm offers silicon startups zero-cost access to the world's most widely used chip designs
- Xilinx, Arm, Cadence, and TSMC Announce World's First CCIX Silicon Demonstration Vehicle in 7nm Process Technology
- Thread Group Takes Leap Forward with Availability of First Certified Software Stacks from ARM, NXP, OpenThread and Silicon Labs; Launches Product Certification Program
- Silicon Creations Taps Silvaco's Custom Design Flow for 10nm FinFET Designs
- Silicon Labs Launches the World's Most Energy-Friendly MCUs Based on the ARM Cortex-M0+ Core
Breaking News
- Ceva multi-protocol wireless IP could simplify IoT MCU and SoC development
- Controversial former Arm China CEO founds RISC-V chip startup
- Fundamental Inventions Enable the Best PPA and Most Portable eFPGA/DSP/SDR/AI IP for Adaptable SoCs
- Cadence and TSMC Collaborate on Wide-Ranging Innovations to Transform System and Semiconductor Design
- Numem at the Design & Reuse IP SoC Silicon Valley 2024
Most Popular
- GUC provides 3DIC ASIC total service package to AI/HPC/Networking customers
- Qualitas Semiconductor Appoints HSRP as its Distributor for the China Markets
- Siemens collaborates with TSMC on design tool certifications for the foundry's newest processes and other enablement milestones
- Credo at TSMC 2024 North America Technology Symposium
- Huawei Mate 60 Pro processor made on SMIC 7nm N+2 process
E-mail This Article | Printer-Friendly Page |