Releases Standard Cell IP for Leading Edge ProcessesNEWARK, Calif. –– March 15, 2004
– Prolific Inc., the leading provider of design optimization and automated standard cell creation software, today announced its entrance into the Semiconductor Intellectual Property (SIP) market with the release of standard cell layout and netlists for .18 micron, .15 micron, .13 micron, 90 nanometer, and 65 nanometer process technologies. The layout can be quickly optimized for multiple foundries in a completely automated fashion, providing customers better control over designs and the fabrication process.
Recent case studies have shown that optimizing standard cell libraries for design requirements, process technologies and specific EDA tools yields double-digit gains in performance, area reduction, and power utilization. For example, simply increasing the drive strength count beyond those provided in general purpose libraries improves area and power utilization. The additional drive strengths also reduce design iterations by providing the correct transistor size for timing.
“This release directly responds to customer requests and is a natural extension of our expertise,” noted Dan Nenni, vice president of marketing at Prolific. “Prolific has created standard cell software and libraries for semiconductor companies around the world for the past nine years.”
“This is a cost effective way for semiconductor companies to take ownership of their library IP and optimize it for their specific requirements,” stated Ewald Detjens, CEO of Circuit Semantics Inc. “We are pleased to be working with Prolific on this offering. Complete and reliable timing, power, noise, and functional models are key to success in both design and manufacturing.”
“Understanding the impact of second-order effects—signal integrity, leakage power, glitch and metastability—on IP performance is crucial,” added Dr. You-Pang Wei, president and CEO of Legend Design Technology. “Integrating the Prolific layout optimization, Circuit Semantics characterization, and Legend Design Technology circuit simulation products provides a total solution so customers can completely analyze these effects.”
“This is an excellent opportunity for semiconductor companies to establish a competitive advantage by taking control of their intellectual property,” concluded Dr. Paul de Dood, CEO of Prolific. “Our customers can rapidly respond to changing design requirements and process changes.”
The Prolific Standard Cell IP is integrated into the Prolific ProGenesis layout generation tool, providing a completely automated solution for the optimization of semiconductor intellectual property. Prolific's ProTiming product can then be used to optimize this SIP at the design level for performance, power, and area.About ProGenesis
Prolific's ProGenesis is the industry standard for fully automated creation of standard cells. Key to the tools' success is their ability to generate better-than-hand-drawn quality results in significantly less time than that of other tools or traditional methods. ProGenesis supports all 1.0 micron to 65nm process design rules, Design For Manufacture (DFM) practices to increase silicon yield and reliability, and sub-wavelength optimization Resolution Enhancement Techniques (RET): Optical Proximity Correction (OPC); Strong and Attenuated Phase-Shift Mask (PSM); Scattering Bars (SB); and Off-Axis Illumination (OAI). ProGenesis is in use by major semiconductor companies around the world. About ProTiming
ProTimingTM is Prolific's block-level optimization tool, working in the synthesis and place-and-route (SPR) flow. ProTiming gives IC designers up to 20% improvement in timing and power, with or without adding new cells to the standard cell library. ProTiming performs design-specific timing optimization during the static timing analysis step of the physical design flow. The software makes use of cells already existing in the library and can provide a 5-10% performance increase without modifying RTL or adding new cells to the library. If desired, ProTiming can also specify new cells that are created as needed, either by traditional methods or automatically by Prolific's ProGenesis® tool suite for an additional 5-10% performance increase. ProTiming is also in use by major semiconductor companies around the world. About Prolific
Based in Silicon Valley, Prolific Inc. provides software to enable the design of today's most demanding integrated circuits optimizing quality of results with respect to timing, power, area and yield, and at the same time reducing overall design time and costs. ProTiming™ is the first commercially available optimization tool integrated into the STA step of the physical design flow. ProTiming gives IC designers up to 20% improvement in timing and power in a no-risk, fully automated and integrated flow. ProGenesis® is the leading software for automatically creating standard cells optimized for design performance, power, area and yield. Founded in 1995, Prolific counts the top semiconductor companies around the world as customers with products silicon prove in .18m through 90nm process nodes. Prolific is headquartered in Newark, Calif., at 39899 Balentine Dr., Suite 380, Newark, CA 94560, telephone (510) 252-0490, fax (510) 252-0491. For more information, visit www.prolificinc.com
ProGenesis is a registered trademark and ProTiming is a trademark of Prolific Inc. Prolific acknowledges trademarks or registered trademarks of other organizations for their respective products and service