SANTA CLARA, Calif. Incentia Design Systems Inc. will announce plans this week to challenge the overwhelming dominance of Synopsys Inc. in ASIC synthesis. The EDA startup believes it has the people, the money and the technology to take on this seemingly daunting task to become a formidable competitor in logic and physical synthesis.
Founded in 1998 by EDA veterans, and fueled by $8.15 million in venture funding, Incentia is already shipping its logic synthesis product to undisclosed customers. The company is promising to ship a physical synthesis product next month. Incentia's technology is based on a fast static timing analyzer that can take in a broader set of constraints than existing synthesis tools, the company said.
Incentia is led by Ihao Chen, president and chief executive officer, who was vice president of engineering at Aceo, a synthesis company acquired by Avanti Corp. in 1998. Chen previou sly held R&D positions at SynTest Technologies Inc. and Cadence Design Systems Inc.
Kevin Xiang, Incentia vice president of engineering, was an architect of synthesis, timing and verification products at Cadence. Shing-Chong Chang, Incentia vice president of product management, was an architect of Avanti's placement and routing products. EDA veteran Paul Huang, winner of last year's EDA Consortium Phil Kaufman award, is an adviser to Incentia.
The company's products are currently named DesignCraft-AVS, which offers RTL synthesis to gates, and DesignCraft-PVS, which generates a fully placed netlist. These product names may change when the company formally announces its products around the time of next month's Design Automation Conference.
Incentia seeks to resolve an existing "timing inconsistency" between synthesis and sign-off, Chen said. "People are using different timing engines for synthesis and sign-off," he said. And even if this i s not true, Chen said, synthesis users have to stick to a small set of constraints so timing engines can run fast enough.
"We can take almost the entire set of constraints used in sign-off," Chen said.
Incentia's products, he said, will also offer faster speed and more capacity than existing tools from Synopsys, Cadence or other providers. Chen declined to offer any benchmarks or make specific claims, but he said benchmark information will be provided with Incentia's June product announcement.
Gary Smith, chief EDA analyst at Gartner Dataquest, doesn't hold out much hope for Incentia. "They're going up against all of the big boys," Smith said. "Any advantages they have are being worked on very hard in back rooms at Synopsys, Cadence, Magma and Monterey. They [Incentia] lack signal integrity, which limits their usefulness in high-speed designs."
Tom Ferry, vice president of marketing for physical synthesis at Synopsys, said his company has heard of Incentia but is unaware of any success the startup has had with customers. Ferry said that synthesis and sign-off engines need to be "tightly correlated" but do not need to be exactly the same software.
"Developing a world-class synthesis product that is usable in a wide variety of designs is very difficult," Ferry said. "A startup may be able to produce a product that works well for a narrow class of designs and design styles, but it would be difficult to match Synopsys' leading-edge technology, robustness, field applications support, ASIC vendor support, user community and infrastructure," he said.
The cornerstone of Incentia's technology is a proprietary static timing analyzer that uses what Chen called an "extended timing exception graph" technology. It's said to handle high-speed, multimillion-gate designs and to offer special timing analysis "modes" not available with existing products.
For example, Chen said, most current synthesis tools use a technique called "time bor rowing" for latch-based designs. In addition to this technique, he said, Incentia offers a unique "pass-through" or "latch transparent" mode that's more intuitive, and offers true slack analysis features.
Incentia promises easy migration from Synopsys synthesis tools. Its offerings take RTL VHDL or Verilog code using the Synopsys language subsets and accept constraints in the Synopsys Design Constraint (SDC) format. They output netlists and placement data that can be taken to Cadence or Avanti layout tools.
Incentia tools either produce a gate-level netlist or a fully placed netlist from RTL code. But the company will offer more than just bare-bones synthesis. Chen said that Incentia has a low-power synthesis option, in addition to optimization for timing and power. He said that the Incentia Parameterized Components library provides functionality like that of Synopsys' DesignWare product, offering components such as multipliers, adders and dividers.
Chen said that Incentia synthesis tools can cre ate and reorder scan chains and check for testability. He said the company offers an engineering change order capability from the netlist level, although not from the register transfer level. Also lacking, for now, is clock-tree synthesis.
Incentia's weakest point now is lack of ASIC library support. The only ASIC vendor offering support is Faraday Technology Corp. Chen said Incentia is talking to major ASIC vendors in an attempt to line up support. Meanwhile, he said, Incentia supports a customer-owned-tooling flow with intellectual property from Artisan Components and Virtual Silicon.
Chen said that Incentia's physical synthesis produces timing estimates that are within 10 percent of post-route results. He said the biggest block that the product has synthesized so far was 500,000 gates. Chen declined to name any customers other than Via Technologies Inc., a Taiwanese semiconductor and systems company.
Incentia said it has already installed 10 licensed, paid copies of its software. The company will release pricing and availability information in June.