Commentary: Spec raises bar for IP and SoC verification
EE Times: Latest News Spec raises bar for IP and SoC verification | |
Thomas L. Anderson (03/18/2004 8:00 PM EST) URL: http://www.eetimes.com/showArticle.jhtml?articleID=18400922 | |
Everyone knows that design reuse is essential for system-on-chip (SoC) development and that functional verification consumes the largest portion of the development process. Reuse of blocks from previous-generation chips or related chips within the same organization is universal, and acquisition of design IP from internal or external sources is quite common among SoC design teams. Although reuse shortens the design time, verification takes 60-80% of the development effort for most SoC projects and functional verification is the dominant task. Most other verification tasks are highly automated; for example equivalence checking and most physical verification steps require relatively little user interaction. However, the process of developing verification models, writing tests, setting up for testbench automation, and debugging test results is enormously time-consuming. | |
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