Latest Release is Industry's First SystemC Based Solution for Hardware/Software Partitioning and Platform Design Automation
SAN JOSE, Calif. March 29, 2004 * * * CoWare Inc., the leading supplier of system-level electronic design automation (EDA) software and services, announced a major new release of its SystemC-based ConvergenSCT system-on-chip (SoC) design tools to speed the concurrent design of SoCs with embedded software. The ConvergenSC product family combines new hardware/software partitioning and platform assembly together with new simulation, debug and analysis capabilities. Together with the ConvergenSC Model Library, the largest IP model library for SystemC, customers are able to rapidly create and validate SoC designs at the transaction level in SystemC. The latest release offers major new functionality using CoWare's patented Interface Synthesis® technology for SystemC.
"The key for SoC design success has moved from RTL to system-level design at higher abstraction levels, which is necessary to realize optimized SoC architectures and early embedded software development. Toshiba has decided to move our next-generation design flow to system-level design using high-level design languages at the transaction level, in order to optimize and explore alternative SoC architectures, perform hardware/software co-design and do early platform-based software development," stated Kosei Okamoto, Executive Quality Leader of the Toshiba Personal Computer & Network Company. "We have been working with CoWare for three years and we are adopting the ConvergenSC design environment for our unified C-based design environment."
Increasing Complexity Challenges for Systems and Semiconductor Companies In the electronics industry, multiple functions-such as communications and multimedia-are increasingly combined in single products. Designing these convergent products quickly-and getting both the hardware and embedded software optimized and functioning together-is an enormous challenge. Architects in both systems and semiconductor companies are finding that current methods fail to handle the complexity of these designs, including the rising amount of embedded software that must be designed and verified with the hardware. These pressures are now driving rapid adoption of electronic system-level (ESL) design methods.
"ConvergenSC helps close the gap being created by advancing semiconductor technology and the limitations of existing design methodologies," said Mark Milligan, vice president of marketing, CoWare. "We now have the standard language for system design-SystemC-plus wide IP model availability, and tools and methodologies that help engineers differentiate by design for competitive advantage."
ConvergenSC Speeds the Design of SoCs with Embedded Software
The new functionality in ConvergenSC includes:
- Hardware/Software Co-Design for SystemC: A top-down design methodology based on Interface Synthesis enables rapid exploration of hardware/software partitioning alternatives and mapping of a SystemC executable specification to reused functions and new blocks. This cuts time spent capturing and validating the specification for highly complex systems, and reduces risk by improving the hand-off to the implementation team.
- Platform-Based Design for SystemC: A platform-based design methodology combines a new graphical design environment and Interface Synthesis with system-level analysis and the ConvergenSC Model Library. Platform architects can now rapidly create, optimize and validate platforms at the transaction-level using SystemC. Additionally, ConvergenSC now automates integration of RTL blocks into the transaction-level system to "divide and conquer" the burgeoning verification task by re-using the SystemC model as a testbench.
- Synthesis of On-chip Interconnect from SystemC: Interface Synthesis automatically generates the RTL implementation for the interconnect from the transaction-level platform model, freeing hardware engineers to concentrate on designing the value-added IP blocks.
- Enhanced Analysis and Debug: ConvergenSC's SystemC-aware debugger now supports multi-threaded designs, and its many system-level analysis views can now be used dynamically during simulation, speeding the debugging and analysis of SystemC designs.
- Faster SystemC Simulation: Delivering on CoWare's commitment to SystemC simulation performance leadership, ConvergenSC simulation runs up to 75% faster than the previous release.
- Expanded Interoperability: New interfaces enable mixed-language simulation with Mentor ModelSim® and Verisity Specman Elite®. ConvergenSC is now interoperable with verification flows from Mentor, Synopsys, Verisity and CoWare's alliance partner, Cadence.
Pricing and Availability
ConvergenSC 2004.1 is available immediately. For pricing information, contact your local sales office or email email@example.com. For more information, visit www.coware.com.
CoWare is the leading supplier of system-level electronic design automation (EDA) software tools and services. CoWare offers a comprehensive set of electronic system-level (ESL) tools that enable SoC developers to "differentiate by design" through the creation of system-IP including embedded processors, on-chip buses, and DSP algorithms; the architecture of optimized SoC platforms; and hardware/software co-design. The company's solutions are based on open industry standards including SystemC. CoWare's customers are major systems, semiconductor, and IP companies in the market where consumer electronics, computing, and communications converge. CoWare is headquartered in San Jose, Calif., and has offices around the world. For more information about CoWare and its products and services, visit http://www.coware.com.
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