PALO ALTO, Calif., March 31, 2004--Denali Software, Inc., the leading provider of electronic design automation (EDA) tools and intellectual property (IP) for chip interface design and verification, today announced that Cadence Design Systems (NYSE: CDN) has selected Denali's PCI Express verification IP for use in its vertical solution for PCI Express. The Denali Verification IP fits seamlessly into the Cadence Incisive™ functional verification platform for the verification of complex SoC designs requiring PCI Express interfaces.
Cadence selected Denali's PureSpec™ verification IP to simulate and verify PCI Express IP cores and devices in Cadence's vertical solution for PCI Express. By using Denali's PureSpec verification IP models, combined with the Cadence Incisive functional verification platform, designers can expose potential bugs early in the development cycle before the designs are implemented in silicon, saving valuable development time and resulting in faster time-to-market with a higher quality end product.
"Denali has become a leading provider of verification IP and technology for complex chip interfaces, like memory and PCI Express," said Tim Henricks, vice president of engineering services at Cadence. "Delivering high-quality PCI Express interfaces for our customers' next-generation chips is a critical task for us. The Cadence vertical solution for PCI Express supports an integrated approach of platform technologies, IP and a comprehensive range of design services to accelerate product development from design to design-in. The Cadence Incisive functional verification platform, combined with Denali IP, provides designers with a powerful and flexible design environment for verifying SoCs with PCI Express interfaces so designers may compress overall verification time and get to market faster."
"Interface verification, for both compliance and interoperability, is playing an increasingly critical role in next-generation chip development flows," said Kevin Silver, vice president of marketing at Denali. "An effective solution must include robust modeling and verification, as well as technology for addressing interoperability-which includes widespread industry adoption. We've accomplished these goals with PureSpec, and it is now the most widely used verification IP solution for PCI Express interfaces. Cadence designers have combined PureSpec with their vertical solution to form a very powerful verification flow for PCI Express designs. For Cadence customers, this translates into a very high quality end product and faster time-to-market. We are pleased to be working with Cadence on this flow, and to further enable PCI Express technology."
PCI Express technology is the new industry-standard I/O targeted to provide local connectivity across desktop, mobile, enterprise, and communications platforms. PCI Express resides at the center of enterprise interconnect innovations anticipated across storage, networking, clustering, and workstations. Next-generation servers utilizing PCI Express technology will offer powerful and cost-effective computing platforms, scalable hardware building blocks, market-tested best-of-breed solutions, and enterprise-class reliability, availability, serviceability, and manageability.
PureSpec is a verification IP product used by chip designers to simulate and verify PCI Express design interfaces. PureSpec models all devices in the PCI Express topology, including the root complex, switch, endpoint, and PCI Express to PCI bridge. Within PureSpec, all protocol layers (physical, data link, transaction) of the PCI Express specification are completely modeled and can be simulated concurrently or independently. The product contains thousands of assertions that are monitored during simulation to ensure compliance with the PCI Express specification and interoperability with other PCI Express devices. The PureSpec product is built on the proven product architecture of Denali's MMAV product, which has been used to verify complex memory interfaces for thousands of successful designs, and provides seamless integrations to all popular EDA tools and verification languages. Proven product platform, dedicated customer support and unmatched EDA modeling and verification expertise make PureSpec the best-in-class verification IP solution for PCI Express designs. The PureSpec product is available now for customer evaluation at: www.denali.com/purespec.
Denali Software Inc. is the world's leading provider of EDA tools and Semiconductor Intellectual Property (SIP) solutions for chip interface design, integration, and verification. PureSpec is the industry leading solution for verifying compliance and interoperability for PCI Express designs. Denali's Databahn memory controller cores are licensed for use in over 80 chips and provide designers with the highest quality solution for interfacing with all new and emerging high-performance memory technologies. Denali's MMAV product is the de facto industry standard for modeling and simulating memory during all phases of design and verification. Memory selection, memory controller configuration, and memory system performance analysis are supported through Denali's online infrastructure at eMemory.com. More than 400 companies worldwide use Denali's tools, technology, and services to design and verify complex chip interfaces for communication, consumer, and computer products. For more information, please visit Denali at www.denali.com or contact Denali directly at: 650-461-7200.
NOTE: Denali, The Denali logo, Databahn, eMemory, MMAV, and PureSpec are trademarks of Denali Software, Inc. PCI Express is a trademark of PCI-SIG. All other trademarks are the property of their respective owners.