The 550 MHz 24K family is ideally suited for performance-hungry applications and cost-sensitive markets, and offers 1.44 Dhrystone MIPS/MHz performance in a core area of less than 3.0 mm2, along with a wide range of configurable features. At the same time, it offers SOC designers broad tool and software support that minimizes development time, risk and cost. Development support includes tailored, front-to-back-end design methodologies and a standard, Open Core Protocol (OCP) interconnect structure. The core family also was designed to be implemented using standard high-performance libraries and on-chip memories from industry-leading companies.
"Since we introduced the 24K microarchitecture just a few quarters ago, we have seen extraordinary interest and demand for the first products," said John Bourgoin, president and CEO of MIPS Technologies. "The combination of high performance in a flexible, synthesizable core coupled with a low system cost point is clearly appealing. We also are pleased with the growing list of leading third parties within the MIPS ecosystem that are optimizing their product offerings for SOC designers and software developers using the 24K core family."
"Performance-driven, cost-sensitive applications will benefit significantly from high performance products such as the 24K core family. It offers SOC designers the headroom needed to create competitive and differentiated products, while giving them the tools to get to market with speed, ease and efficiency," said Tony Massimini, chief technologist at market research firm Semico Research.
Performance Headroom
The 24K cores are ideal for engineers who need to keep costs down while adding more features and functionality to next-generation SOCs. High-performance, programmable processors give a design more headroom so that future upgrades can be implemented in software. The 24K cores also offer the features and flexibility to meet the needs of today's most demanding applications. For example:
Key Features
The number one feature of the 24K family is high performance. To yield high frequency, the 24K family is based on an 8-stage pipeline. A full cycle is allocated to the instruction and data cache access to enable performance scalability across a wide range of technologies. Sophisticated hardware branch prediction is present to keep the pipeline supplied with instructions. The memory subsystem was designed with high performance in mind. Four load misses may be outstanding and are processed by a 64-bit connection to the OCP interface standard.
The 24K core interface is standardized on OCP on-chip interconnect technology defined by the Open Core Protocol International Partnership (OCP-IP). Designers who choose to utilize OCP can build their cores independent of specific bus protocols and easily reuse OCP-compliant cores across multiple SOC designs, thus reducing development time and lowering risk and costs. They also can take advantage of MIPS Technologies' SOC-itâ„¢ system-level controller optimized for OCP. The SOC-it OCP controller provides a tightly coupled memory controller and includes a bridge to other on-chip system buses, thus reducing subsystem memory latency and increasing system throughput.
| Specifications: | ||
| Process | 0.13-micron | |
| Frequency | 400-550 MHz (worst case) | |
| Performance | 576-792 Dhrystone MIPS | |
| Core size | less than 3.0 mm2 for a 24Kcâ„¢ core | |
Development Support: The MIPS® Ecosystem
To minimize the system-level design effort, MIPS Technologies has teamed with a broad range of industry-leading companies to provide customers with the development tools and software they need to quickly bring their MIPS-Basedâ„¢ designs to market. For example:
Artisan Components' high-speed SAGE-HSâ„¢ standard cell libraries were used to help validate the performance of the 24K core family.
Cadence Design Systems' Encounterâ„¢ Reference Methodology is available for customers of the 24K core family and provides customers with a fast, predictable path to high-quality silicon.
Green Hills Software recently announced a total software development solution that employs leading-edge compiler technology optimized for the 24K microarchitecture.
Mentor Graphics recently announced that the VStationâ„¢TBX Accelerator was used to help verify the industry-leading performance of the 24K core family. Also, Mentor announced the availability of its Seamless® Hardware/Software Co-Verification solution for the 24K family, which enables designers to validate hardware/software interfaces in a virtual prototype prior to fabrication of the design.
Microsoft's latest version of Windows CE .NET version 4.2 runs on the 24K core family. A board support package (BSP) is available from the MIPS Technologies Website.
MIPS Technologies' Software Toolkit combines the popular Free Software Foundation (FSF) Open Source GNU tools with MIPS Technologies' proprietary runtime libraries that are pre-configured to many of its popular evaluation boards. The MIPS software development environment (SDE) supports the latest features of the 24K core family. The MIPS SDE-lite package is available for free download from www.mips.com.
MontaVista Software is working with MIPS Technologies to ensure that its MontaVista Linux solution is optimized and tuned for the 24K core family.
OCP-IP, the industry association dedicated to making a common standard for IP core interfaces that facilitate "plug and play" SOC design, defined the on-chip interconnect technology that is employed as the native interface for all 24K cores.
Synopsys' optimized Galaxyâ„¢ Design Platform reference flow is available for customers of the 24K core family, which will help customers meet their performance targets quickly.
Virage Logic Corporation's high speed, power efficient ASAP memory product line was used to demonstrate the 550 MHz performance of the 24K core family.
Wind River Systems' VxWorks real-time operating system will provide a foundation that can be extended with Wind River's market specific PLATFORM.
About MIPS Technologies
MIPS Technologies, Inc. is a leading provider of industry-standard processor architectures and cores for digital consumer and business applications. The company drives the broadest architectural alliance that is delivering 32- and 64-bit embedded RISC solutions. The company licenses its intellectual property to semiconductor companies, ASIC developers and system OEMs. MIPS Technologies and its licensees offer the widest range of robust, scalable processors in standard, custom, semi-custom and application-specific products. The company is based in Mountain View, Calif., and can be reached at +1 (650) 567-5000 or www.mips.com.