Mentor, Synplicity prep programmable platforms

Mentor, Synplicity prep programmable platforms
By Michael Santarini, EE Times
April 30, 2001 (1:22 p.m. EST)
URL: http://www.eetimes.com/story/OEG20010427S0090

SAN MATEO, Calif. — FPGA synthesis-tool rivals Synplicity Inc. and Mentor Graphics Corp. are aggressively bidding to become the quintessential tool vendor for the emerging — and potentially lucrative — market for platforms that assist the development of designs featuring a complex core flanked by programmable logic.

Indeed, Mentor Graphics' Seamless Co-verification Group is slated to launch a virtual-prototyping tool, tentatively called Platform Express, sometime after the Design Automation Conference in June, EE Times has learned. The tool promises to facilitate the hardware and software co-design and co-verification of so-called programmable platforms.

Synplicity, meanwhile, is planning a standard-cell tool that is thought to be aimed squarely at this emerging market — one that Joe Gianelli, director of channel marketing at Synplicity, called "a huge growth opportunity" for FPGA tool vendors. Synopsys Inc., too, hi nted it would extend support for programmable platforms.

But just what role EDA vendors will actually play in a market where platform suppliers like Altera Corp. and Xilinx Inc. hold fast to internal tool development remains to be seen.

Field-programmable gate array vendors like Xilinx and Altera, along with their brethren in ASICs, are betting big on the programmable platform, a methodology in which "star" cores, such as microprocessors, anchor an array of surrounding specialty logic to attack a given application. The concept will entail a whole new tool chain and methodology, the EDA vendors believe — one that could help customers bring programmable-platform-based designs to market faster, while also delivering higher margins to a slow-growth software business.

"These processor-based FPGAs are taking that business to the next level," said Synplicity's Gianelli . "It is probably the most important change in the FPGA industry since its inception."

Gary Smith, chief EDA analyst at Gar tner Dataquest, agreed that programmable platforms will be a huge market for silicon and could open new doors for EDA, once "the vendors figure out the real problems of this new area." Smith sees verifying hardware and software together as the biggest challenge, and said he is encouraged that Mentor is addressing it early.

Moreover, industry watchers said, the new methodologies for programmable-platform design are untried, a fact that will make life harder for EDA companies. In addition, tool vendors are not likely to find receptive partners on the programmable-logic side, where companies have devised their own key point tools for their proprietary architectures — and given them away, largely for free. "In many ways we are further ahead of EDA vendors in terms of tool sophistication, especially in place and route," said Rich Sevcik, senior vice president of software and cores for Xilinx.

And lurking in the background is the EDA industry's old demon: failure to close the gap between ASIC perform ance and tool utility. "In the ASIC world, they relinquished just about all tool development to the EDA industry," said Sevcik, referring to the design gap in which tools lag process development. "There is no such thing as a 'design gap' in programmable logic, and we want to keep it that way."

Takeover time

But in the view of Dataquest's Smith, "FPGA vendors have subsidized tools for too long — they really need to step away from tool development and let the EDA guys take over." Smith sees Mentor as "one of the only companies that has the software experience to go after the intelligent testbench at a true system level."

In fact, the biggest push in this early market is coming from Mentor, whose officials confirmed that the coming Platform Express product is one of many offerings the Wilsonville, Ore., company has planned for the programmable-platform sector.

Mentor Graphics executives were reluctant to give up details of Platform Express but said the tool will facilitate quic kly attaching cores and blocks of logic to platforms produced by FPGA, ASIC and system houses. John Wilson, business development manager at Mentor, said the tool will guide system designers through hardware and software partitioning and automatically suggest and set up verification environments for both hardware and software. It will also link up with Mentor's traditional hardware design and verification tools, and with embedded-design software, said product line director Michael Chen.

The product will complement a bevy of ASIC tools for both design and verification that Mentor has tailored over the last couple of years for designers moving to programmable logic. Now, "We are pushing very hard in this area [of programmable platforms]," said Tom Feist, group director for synthesis marketing at Mentor's Exemplar Logic group. "We think programmable platforms are going to open up all kinds of innovation out there. The way we look at it is, the garage shop guys can get back to innovating again."

Likewise , Bernie Aronson, Synplicity's president and chief executive officer, confirmed to Wall Street analysts during a recent conference call on earnings that the Sunnyvale, Calif., company is developing tools for standard-cell design, seemingly to accommodate the mix of programmable logic and standard cells on the hybrid platform chips. The company has also made several alliances with programmable-platform vendors and has taken a stake in Adaptive Silicon Inc., which offers a programmable-logic core that can be embedded on standard-cell processes.

Two paths, same destination

This new opportunity has programmable-logic and ASIC vendors converging, addressing the same market from different sides. PLD vendors like Altera, Xilinx and Actel plan on offering star cores pre-implemented on silicon and surrounded by blocks of programmable logic. At the same time, ASIC companies such as LSI Logic Corp. will be adding cores of programmable logic, like those offered by Adaptive Silicon, to their standard-c ell architectures.

"Processor development and hardware designers have been two separate groups," said Jackie Patterson, director of marketing for Synopsys' FPGA group. "It will be interesting to see if these [platform] chips are designed by a new breed of designer with both skills, or if it will still take two separate groups."

Synplicity's Gianelli declined to elaborate on the company's upcoming offerings for standard cell, but said Synplicity sees great opportunity for tool vendors in this migration. Not only will designers need new tools, he said, but they will also have to develop new methodologies and be trained to use programmable platforms. "We are very focused on looking at what is happening inside the silicon and how we can better serve these new technologies," said Gianelli.

Synplicity has announced deals to work with Altera, Xilinx and Adaptive Silicon to develop synthesis tools for their flows, one of the few niches where FPGA vendors welcome third-party offerings. The company, more than any other publicly traded EDA firm, has until recently been deemed a point-tool specialist fielding synthesis for FPGAs, a market long limited by the commonly held belief among users that FPGA tools should be low-cost or no-cost.

This idea has been perpetuated in the main by FPGA tool vendors themselves, which offer their own flavor of tools for free or offer OEM versions for a few thousand dollars, seeing the big payoff in volume silicon.

Sevcik at Xilinx said PLD makers learned well from the mistakes made by ASIC houses more than a decade ago, and prefer to roll their own tools. FPGAs' big selling point over ASICs is time-to-market, he said. "And if we had to rely on EDA vendors to create tools for our architectures, we would likely lose that advantage."

Still, "We are becoming increasingly reliant on third-party partners for certain pieces of our tool flow, such as synthesis and behavioral simulation," said Dave Greenfield, director of development-tools marketing at Altera. "But we thin k we have to be involved in tool development and have to keep ownership of the place and route piece — we need to control our own destiny."

Gianelli pointed to the ASIC houses' programmable platforms as a potential market more accustomed than FPGA vendors to third-party tools — and one not shy about paying $50,000 or more for a tool.

Mentor and even Synopsys see programmable platforms as a way to raise average selling prices to a point somewhere between high-end FPGA tools and mainstream ASIC tools.

Possible spoiler

But Gianelli and Mentor's Feist view Synopsys as a spoiler in the FPGA space, OEMing its lower-end, FPGA Express push-button tool to PLD vendors at little cost. "Our competitors have OEM deals also and there is nothing preventing them from entering into more," countered Synopsys' Patterson. She noted that the pricing of the company's high-end FPGA synthesis tool, FPGA Compiler, is in line with high-end offerings from Synplicity and Exemplar.

Synopsys has indicated an interest in tools for reconfigurable-platform design via its semi-secretive Nimble Compiler project. As for programmable platforms, "I didn't think it would be news to designers that Synopsys is going to offer tools for designing chips that have microprocessor cores on them," Patterson said.