Faraday Introduces Microprocessor-Optimized SRAM

1GHz SRAM Enables UMC Customers to Integrate 500+ MHz CPUs into Next Generation SoCs

SUNNYVALE, California, and HSINCHU, Taiwan, April 12  -- Faraday Technology Corp. (TAIEX: 3035), a leading fabless ASIC and IP provider, today announced its ultra-high-performance 0.13um SRAM Compiler. The synchronous single-port SRAM compiler is optimized for SoC designs which embed high speed synthesizable processor cores such as ARM10, ARM11, and MIPS 24K. The silicon proven SRAM for the UMC 0.13um HS process will be available in May, 2004.

"I am very excited about the first product from our new SRAM technology," said Hsin Wang, Associate Vice President of R&D at Faraday. "It delivers tremendous differentiation at the system level, and shows that our team understands how to deliver compelling solutions, not just raw technology."

While most typical ASICs in today's 0.13um technology still run at less than 333 MHz, ever popular synthesizable CPU cores have made big claims about reaching speeds in excess of 500 MHz. As Microprocessor Report analyst Markus Levy stated aptly in his August 3, 2003 article, "Despite the engineering efforts applied by both ARM and MIPS, the operating frequency of the synthesizable ARM11 and the [MIPS] 24K will always be limited by the available memory technology." The problem is worsened by the fact that CPU has MUX logics and needs extra timing margin to handle wire delay, clock uncertainty, hold time, testability, etc. All together, only two-thirds of a clock cycle is left for the memory. In other words, for designers who are looking for 500 MHz embedded processors, 750 MHz SRAM blocks are needed. "That's why Faraday provides the high-speed microprocessor-optimized SRAM compiler for them to achieve desired chip performance," Hsin Wang added.

Faraday's New SRAM Technology

In order to achieve faster memory speeds, Faraday incorporated several new design techniques in the SE memory compiler. First, the sense amplifier circuit provides much tighter timing control by employing a new self-time logic to trigger at just the right time. Second, brand new architecture was adopted for speed enhancement. Lastly, Faraday minimized the peripheral circuitry by 50% to reduce power dissipation and design area, and reduced memory cell bit-line capacitance to enhance speed. These technological advances enable a 1Kx128 (a popular configuration for 32KB cache memory) single-port memory to operate at over 750MHz (1.33ns cycle time) under worst case conditions. Smaller configuration can well reach 1GHz in UMC 0.13um HS process.

Availability and Pricing

THE FSC0H_D_SE SRAMs are available on UMC's 0.13um 1.2V High-Speed (HS) logic process. A design kit for SE is ready now and test chips will be available in May 2003 for customer verification. The SE ultra-high-speed memory blocks are available with prices starting at $25,000 per instance, or $150,000 for the SE compiler. The SRAM design kit includes: Verilog simulation model, Synopsys model, memory BIST RTL code, and all related documentation. In addition, IP customers will receive: P&R model, SPICE Netlist, and GDSII database.

About Faraday Technology Corporation

Faraday Technology Corporation is a leading silicon IP and fabless ASIC vendor. The company's broad IP portfolio includes 32-bit RISC CPUs, DSPs, PHY/Controllers for USB 2.0, Ethernet, and Serial ATA. With more than 500 employees and 2003 revenue of $111 million, Faraday is one of the largest fabless ASIC companies in the Asia-Pacific region, and it also has a significant presence in other world-wide markets. Headquartered in Taiwan, Faraday has service and support offices around the world, including the U.S., Japan, Europe, and China. For more information, please visit: http://www.faraday-tech.com

SOURCE Faraday Technology Corp.

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