DDR4/ LPDDR4/ DDR3L PHY IP - 3200Mbps (Silicon Proven in TSMC 12FFC)
New Multimedia Accelerator Features Imagination Technologies' PowerVR Cores
The Intel 2700G multimedia accelerator incorporates a PowerVR MBX graphics core and PowerVR video acceleration and display processing cores from Imagination Technologies.
Said John Metcalfe, VP business development [PowerVR], Imagination Technologies, "With the Intel 2700G multimedia accelerator, Intel is adding important new graphics and video capabilities to handheld computing devices, which together with supporting full VGA resolutions will help re-invigorate this market sector."
The Intel 2700G Multimedia Accelerator chip is available for sampling by customers now and will be in volume production later this year.
|
Imagination Technologies Group plc Hot IP
Related News
- Imagination Technologies' PowerVR MBX Graphics Accelerator Technology Used in Freescale's MPC5121e Processor
- Imagination Technologies' PowerVR SGX Graphics Accelerator Technology Used in Texas Instruments OMAP 3 Platform
- Imagination Technologies' PowerVR IP Incorporated in Freescale Multimedia Processor for Mobile Entertainment Devices
- Imagination's GPU and AI Accelerator Licensed for the latest AIoT RISC-V-based applications
- Imagination's GPU selected by SemiDrive for automotive chip
Breaking News
- IAR Systems fully supports the brand-new Industrial-Grade PX5 RTOS
- Axiomise Accelerates Formal Verification Adoption Across the Industry
- Fluent.ai Offers Embedded Voice Recognition for Cadence Tensilica HiFi 5 DSP-Based True Wireless Stereo Products
- intoPIX to feature TicoXS FIP technology for premium 4K & 8K AVoIP wireless AV at ISE 2023
- Sevya joins TSMC Design Center Alliance
Most Popular
- Weebit Nano nears productisation, negotiating initial customer agreements
- Cadence Quantus FS Solution, a 3D Field Solver, Achieves Certification for Samsung Foundry's SF4, SF3E and SF3 Process Technologies
- Sevya joins TSMC Design Center Alliance
- Avery Design Systems and CoMira Announce Partnership To Enable UCIe-Compliant Chiplet Design
- Open Compute Project Foundation and JEDEC Announce a New Collaboration
![]() |
E-mail This Article | ![]() |
![]() |
Printer-Friendly Page |