MOSYS' 1T-SRAM EMBEDDED MEMORY VERIFIED ON 0.13-MICRON LOGIC PROCESS Ultra-dense embedded memory technology features dramatically superior soft error rate
SUNNYVALE, CA (April 23, 2001) - MoSys, Inc. announced today that it has completed silicon verification of its ultra-dense 1T-SRAM embedded memory technology on TSMC's 0.13-micron standard logic process. The patented ultra-dense memory technology delivers dramatic production benefits in cost and yield compared to traditional six transistor embedded SRAM and is now silicon-proven for the latest generation logic process.
As designers are increasingly challenged by requirements for high reliability combined with lowest cost, 1T-SRAM memory technology delivers a measured soft error rate of 1000 FITs/Mb that is more than an order of magnitude better than six transistor SRAM at the 0.13-micron process generation. As a result, designers may be able to avoid using costly error correction techniques that may be required by applications using traditional SRAM on the same process.
"1T-SRAM embedded memory is already proven in volume production using three earlier process generations and is now available on the 0.13-micron process; the choice for next generation products" commented Mark-Eric Jones, MoSys? vice president and general manager of intellectual property. "It is also demonstrating superior reliability and scalability as process technology advances to finer geometries".
MoSys' patented 1T-SRAM technology offers a combination of high density, low power consumption, high speed and low cost unmatched by other memory technologies. The single transistor bit cell used in 1T-SRAM technology achieves much higher density than traditional four or six transistor SRAMs while using standard logic manufacturing processes. No changes are required to standard logic processes when implementing the 1T-SRAM embedded memory. 1T-SRAM technology also offers the familiar, refresh-free interface and high performance for random address access cycles associated with traditional SRAMs. In addition, this technology can reduce operating power consumption by a factor of four compared with traditional SRAM technology, contributing to making it ideal for embedding large memories in System on Chip (SoC) designs. 1T-SRAM technology is in high volume production in SoC products from MoSys' licensees. The high density of 1T-SRAM memory results in dramatic silicon area savings and manufacturing yields that are much higher than traditional six transistor memories. The high yield is further enhanced by built-in redundancy.
Founded in 1991, MoSys develops, licenses and markets innovative memory technology for semiconductors. MoSys' patented 1T-SRAM technology offers a combination of high density, low power consumption, high speed and low cost unmatched by other memory technologies. MoSys provides 1T-SRAM technology as licensable intellectual property to designers who want to efficiently embed large memories in their System on Chip (SoC) designs and also as stand-alone memory devices shipped in volume by MoSys. Licensees that are adopting 1T-SRAM technology include tier one electronics, semiconductor and foundry companies. MoSys is headquartered at 1020 Stewart Drive, Sunnyvale, California 94085. More information is available on MoSys' website at http://www.mosys.com.
Note for Editors:
1T-SRAM is a trademark of MoSys, Inc. All other trademarks or registered trademarks are the property of their respective owners.