Faraday Announces 500 MHz FA626 ARM CPU Core
Hsinchu Taiwan, and Sunnyvale CA, April 26, 2004 - Faraday Technology Corporation (TAIEX: 3035), a leading fabless ASIC and IP company, today announced its next generation ARM CPU core, the FA626. Based on UMC's 0.13um Fusion process, the FA626 delivers 500 MHz worst case in performance, easily making it the fastest merchant ARMv4 CPU core by a factor of two to three. At the same time, it dissipates only 0.6 mW/MHz operating at 500 MHz and 700 uA in standby mode, making it one of the most power-efficient processors. The first customer shipment (FCS) date for the FA626 will be at the end of August, 2004.
"We are very excited about this pacesetting processor development," said Dr. Chi-Yi Hwang, VP of R&D and Marketing of Faraday Technology. "The FA626 will open up new market applications for the most popular 32-bit embedded microprocessor architecture".
Indeed, ARM CPU based customer specific chips account for over 50% of the revenue shipment of a three billion dollar market, according to a recent report by InStat/MDR. New architectures such as ARM11 will likely increase the ARM family's market share leadership. However, for applications which do not rely on rich instruction set extensions but instead require a very high clock speed, Faraday sees a market opportunity not easily filled by currently licensable CPU cores. This is the market motivation for the FA626. The FA626 delivers a CPU with the performance level of MIPS24K, PowerPC 440, and other high speed embedded CPUs, but with the popularity of the ARM instruction set architecture.
Innovative Approaches to FA626 Development
The FA626 features many familiar characteristics in today's highest end 32-bit embedded RISC processor cores, such as eight-stage pipeline, 32KB each of instruction cache and data cache, branch target buffer (BTB) and non-blocking loads, all of which contribute to its outstanding performance of 1.35 Dhrystone MIPS/MHz. But two other development approaches set the FA626 apart from other high performance microprocessors.
First, Faraday has created a high speed ASIC SRAM compiler tailored for microprocessor applications. The new compiler can generate large enough SRAMs to support 32KB of cache memories, with all the margins required by ASIC methodology to run the FA626 at 500 MHz, worst case.
Second, Faraday has optimized the FA626 for UMC's 0.13um multiple-threshold voltage (Multi-Vt) process called Fusion. The oxide implant on the transistor determines its threshold voltage-the lower the voltage, the faster the transistor. The drawback with low Vt, though, is that the standby power dissipation increases, making it undesirable for low power battery operated applications. The FA626 inter-mixes two different Vts throughout the processor complex, high Vt for non-critical path circuits, and low Vt for the critical paths. As a result, the FA626 processor reaches 500 MHz worst case, while dissipating acceptably low standby current.
Platform Architecture Features
The FA626's innovation doesn't stop at the CPU core itself. Several features have been added to maximize its application level performance.
First, the FA626 breaks the tradition of using ARM's AMBA bus for CPU-to-memory interface with its own switch-fabric, called M-Hub. The M-Hub is a 64-bit, 166 MHz synchronous bus interface optimized for DDR333 DRAM. Since the fabric creates point-to-point connection among its masters, the bandwidth is scalable to support high performance network and video interfaces anticipated by the FA626 applications. The M-Hub uses different bandwidth and latency filters to allow each master to request guaranteed performance from the DDR DRAM. The customer can connect an additional level-two cache to increase the available memory bandwidth. An AHB/APB bus bridge is also available to ensure access to a wide range of peripheral devices.
Another innovation of the FA626 is the cache coherency engine, which sits centrally at the DDR DRAM controller instead of at each of the bus masters. Traditional high performance CPUs have implemented cache coherency locally at each CPUs. But in the SoC era, where some of the coprocessors such as H.264 accelerators or IP packet accelerators are created by customers themselves, local coherency means customers would have to implement the same complex and difficult to verify coherency protocol in their accelerators. The FA626 solves the problem elegantly by moving the coherency engine next to the DRAM controller, thereby ensuring consistent data for the entire memory space without requiring virtually any additional work from customers.
"From the customer's perspective, the FA626 is truly a breakthrough product," said Mr. Frankwell Lin, Sales Vice President of Faraday Technology. "It creates a highly differentiated product in the ever so important piece of the puzzle for the SoC market. We expect the FA626 to further Faraday's position as a leader in this space."
Specification, Pricing and Availability:
Faraday's FA626 is available as a CPU platform solution. The UMC 0.13um Fusion version will be available in August, 2004. The list price for a single use licensing is $500,000, and it includes the FA626, the coprocessor interface, the DDR controller, and cache coherency engine with streaming cache, and a Phase Lock Loop (PLL). The FA626 has a configurable cache size of 8KB to 32KB. The UMC 0.18um version of the FA626 will be available in the second half of 2004.
About Faraday Technology Corporation
Faraday Technology Corporation is a leading silicon IP and fabless ASIC vendor. The company's broad IP portfolio includes 32-bit RISC CPUs, DSPs, PHY/Controllers for USB 2.0, Ethernet, and Serial ATA. With more than 500 employees and 2003 revenue of $111 million, Faraday is one of the largest fabless ASIC companies in the Asia-Pacific region, and it also has a significant presence in other world-wide markets. Headquartered in Taiwan, Faraday has service and support offices around the world, including the U.S., Japan, Europe, and China. For more information, please visit: http://www.faraday-tech.com
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