Accelerates adoption of RapidIO protocol into wide range of applications including ATCA Backplanes and Wireless Infrastructure
DALLAS, Texas, April 26, 2004 - At the Motorola Smart Network Developer Forum (SNDF) today, Xilinx, Inc. (NASDAQ: XLNX) announced immediate availability of a new RapidIO Serial Endpoint intellectual property (IP) core. Coupled with Xilinx' parallel RapidIO endpoint IP core and PCI Industrial Computer Manufacturers Group (PICMG)-compliant AdvancedTCA Development platform, this combination provides the industry's only complete FPGA-based solution. Xilinx' enhanced offering allows systems designers to leverage the advantages of a standards-based approach that simplifies development, reduces risk and accelerates time to market for a wide range of high performance applications. Xilinx is demonstrating its RapidIO and AdvancedTCA solutions at the SNDF event in Dallas, Texas starting today through April 29, 2004 About Xilinx
"RapidIO is being designed in at a very rapid rate by leading vendors since they see the advantage of using a standards-based interconnect rather than proprietary options," said Sam Fuller, president of the RapidIO Trade Association. "The new solution from Xilinx will enable these OEMs to get their products out to market quickly and benefit from overall system cost savings."
Fully compliant with the RapidIO Serial Interconnect Specification v1.2 including Errata 1 from the RapidIO Trade Association, the new Xilinx solution implements all three layers of the specification - physical, logical and transport - by leveraging the 3.125Gbps RocketIO™ transceivers and industry's highest performance fabric with Xilinx' flagship Virtex-II Pro series platform FPGAs.
"Wireless infrastructure applications require a serial interconnect driven by need for low pin count, backplane connectivity and bandwidth scalability. RapidIO Serial is a stable, proven, highly scalable technology with the right data rates designed for the embedded space," said Mark Aaldering, senior director of the IP Solutions Division at Xilinx. "We believe that a combination of high performance FPGAs with a RapidIO Serial interface is an ideal solution for designers seeking to implement such systems in short order."
Xilinx RapidIO Endpoint LogiCORE
The Xilinx RapidIO IP Endpoint LogiCORE uses the Xilinx Smart-IP™ technology to reach the 3.125 Gbps line speeds. The complete endpoint solution consists of the Xilinx Serial RapidIO Physical Layer core, the Xilinx Logical I/O and Transport Layer core, Register Manager Reference Design and Buffer Reference Design and is fully compliant with the RapidIO Serial Interconnect Specification v1.2 including Errata 1.
The Serial RapidIO Physical Layer supports one lane operating with 64-bit internal data path and meets the required electrical and timing parameters for all three baud rates, 1.25, 2.5 and 3.125 Gbps line speeds as defined in the Serial RapidIO AC electrical specification. Additional highlighted features include packet retry time-of-day sync, stomp, transmission error recovery, throttle based flow control, multi-cast events and CRC.
Pricing and Availability
The RapidIO physical, logical and transport layer cores are available now from Xilinx as LogiCORE™ products under the terms of the SignOnce license agreement. The site license for both the 8-bit LVDS Physical layer and the Serial 1x Physical layer core LP (Link Protocol)-LVDS is priced at $15,000 and for the Logical I/O and Transport layer core at $10,000. These cores support Xilinx Virtex-II Pro FPGAs using the latest ISE 6.2i design software. Complete information about the Xilinx RapidIO solution is available at http://www.xilinx.com/serialsolution.
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