Xilinx Completes Successful UNH Interoperability Testing For Ethernet Solutions Suite With Virtex-II Series FPGAs

SAN JOSE, Calif., May 10, 2004 - Xilinx, Inc. (NASDAQ: XLNX) announced today that its Ethernet solutions suite has successfully completed interoperability testing at the University of New Hampshire's Interoperability Lab (UNH IOL). Xilinx, the leading provider of programmable logic solutions, is working with the UNH IOL to ensure that its Ethernet offering provides systems designers with the highest probability of first-time design success and design portability, while also reducing hardware testing requirements.

Interoperability tests for Xilinx's Ethernet offerings were conducted with networking equipment incorporating standard Ethernet devices. Xilinx's Media Access Controller (MAC) cores for all three classes of Ethernet were tested: 100 Mb Ethernet, Gigabit Ethernet and 10 Gigabit Ethernet. The intellectual property (IP) cores were tested for standards conformance as well as interoperability, as outlined in the IEEE 802.3 family of standards, using Xilinx Virtex-II Series Platform FPGAs with development boards from Xilinx and its partners.

"The industry-wide success of Ethernet hinges on thorough testing of device conformance and interoperability," said Bob Noseworthy, technical director at UNH-IOL. "Xilinx's commitment to prove out their solutions, including UNH-IOL testing, demonstrates their desire to bring the best, most interoperable, solution to the market."

"We're extremely pleased to have completed this rigorous testing for our popular Ethernet cores," said Mark Aaldering, senior director of IP Solutions at Xilinx. "UNH provides a tremendous service to the industry because it allows companies like Xilinx to offer low-risk IP solutions with a pre-validated level of performance and interoperability. This means systems designers can be confident that their Xilinx FPGA-based designs will work seamlessly with standard Ethernet devices and third-party equipment."

Complete Ethernet Solutions Suite
Xilinx's Ethernet solution includes Layer 2 data link MAC IP cores for 10 GbE, 1 GbE and 10/100 Ethernet interfaces, with a variety of Layer 1 physical layer interfaces including XAUI, 1000BASE-X PCS/PMA, and XGMII, GMII, MII and RMII. All three MACs support Virtex-II series FPGAs. The 1GbE and 10/100 Ethernet MAC cores also support Spartan-IIE and Spartan-3 devices.

The cores are provided through the Xilinx Core Generator in ISE or through Xilinx Platform Studio (XPS), included with the Xilinx Embedded Development Kit. The deliverables include Verilog and VHDL simulation models, timing constraint files, sample compile scripts to aid implementation, as well as a variety of application reference design and development board options and world-class technical support.

For more detailed information about Xilinx's 10 GbE, 1 GbE and 10/100 Ethernet MAC solutions, visit: http://www.xilinx.com/systemio/interop/index.htm.

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