Newest release of the SYSTEMware™ Family provides transaction-based support of SystemC
targeting simulation, hardware acceleration and emulation
Woburn, Mass. - May 18th, 2004 - Zaiq Technologies, Inc., a leading provider of complete design engineering solutions, today announced the release of the newest version of its Pre-configured Reusable Environment and testing Platform (PREP™). PREP provides chip and system designers with a pre-configured verification environment for complex designs, along with a methodology to comprehensively and efficiently test those designs. PREP 4.5 improves upon Zaiq's previous versions of the PREP environment by adding support for the Open SystemC Initiative (OSCI) SystemC and the SystemC Verification Library (SCV).
"As design complexities continue to increase, higher level languages and extensions have emerged to provide additional modeling and verification capabilities. Customers need the flexibility to utilize multiple languages such as SystemC, Verilog and VHDL and a verification environment that enables them to target the most effective verification approach," said Bernard Gilbert, Zaiq's President and CEO. "SYSTEMware, and our new release of PREP, builds upon our proven retargetable transaction-based environment and verification IP. Customers can now incorporate SystemC code, or integrate 3rd party SystemC models directly into the verification environment while maintaining their ability to seamlessly retarget their test benches to the appropriate simulation, acceleration or emulation engine. By using SYSTEMware, customers can save months of environment development, test writing and test bench execution time."
"By adding OSCI SystemC support, our SYSTEMware Environment now provides additional high level hardware constructs and behavioral modeling features to facilitate Electronic System Level verification and co-simulation," noted Richard McAndrew, Zaiq's Executive Vice President of SYSTEMware Products and Services. "Our support of the SystemC language and SystemC Verification Library, SCV 1.0 provides constraint based test randomization, dynamic thread support like fork and join, variable and transaction recording and additional data structures like bags and sparse arrays. In addition to OSCI SystemC, we plan to support EDA vendor extensions in simulation, acceleration and emulation tools from vendors like Cadence, Mentor, Synopsys, Aptix and EVE."
As part of Zaiq Technologies SYSTEMware family, PREP allows rapid deployment of DV environments for projects with an initial pre-configured environment. PREP supports unit, chip and system-level testing, including constrained randomized testing, which results in increased test coverage and greater product viability. PREP's standard verification environment facilitates verification IP reuse and provides powerful, reusable support libraries. PREP supports Verilog, VHDL, C/C++ and SystemC standard usage and tools, and can interface with languages like Vera, System Verilog, and e.
About ZAiQ Technologies, Inc
Zaiq Technologies, Inc. enables its customers to meet critical product development objectives by offering a complete line of specialized design and verification products and services. Zaiq is a recognized leader in system level design and verification for complex, high-performance, system-on-chip (SoC), ASIC and FPGA based systems. The Company's innovative domain-specific design methodologies enable the creation and integration of reusable IP. As a result, customers are able to achieve breakthroughs in the time-to-market and time-to-revenue delivery of complex systems. Zaiq Technologies was founded in 1996 and has completed well over 400 assignments.
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