Paris, France, 01 June 2004
– M2000 today announced that its FlexEOSTM embedded FPGA technology has been successfully manufactured on a test chip in CMOS 0.13µm technology. This means that a ‘silicon-proved’ FPGA macro is now available to ASIC designers who want to add ‘on-silicon’ logic programmability to a design. Many fields of application can benefit from this technology, including wireless infrastructure equipment, security, printers, automotive, set-top-boxes, HDTV, and imaging.
"FlexEOS embedded FPGA macros use proprietary developments of the latest technology to achieve architectural density which is design-proven", said Gabriele Pulini, Vice President for Marketing and Sales at M2000. He went on to add that, "among the major benefits that FlexEOS cores bring to ASIC design, one of the first is competitive advantage by making products flexible. Designers can now change the logic functions of an ASIC, or add new ones, using simple software tools. Secondly, a single Platform ASIC can now be designed to support future product evolutions with no additional NRE investment."
Frederic Reblewski, President and co-founder of M2000, remarked that “FlexEOS uses an innovative architecture designed for full and fast reprogrammability. Its high density gives optimized silicon area, low consumption and high speed. The I/O interfaces are completely flexible”. He also insisted that “an efficient and flexible software flow is as important as optimized hardware architecture, both when integrating the macro on silicon, and also when customizing the macro in a specific application environment. FlexEOS macros come with a state-of-the-art software tool suite for rapid compilation of new applications which can then be dynamically loaded into the FlexEOS core.” About FlexEOS embedded reprogrammable cores
FlexEOS cores are hard macros available in different sizes, and which are portable to any silicon technology. Their logic consists of an array of SRAM based Multi Function logic Cells (MFCs), reprogrammable structures which contain a 4-input Look-Up Table (LUT) and a flip-flop. A multi-level routing hierarchy interconnects the MFCs.
All the core I/Os are symmetrical so that a predefined I/O placement is never a constraint when mapping a new function. Any input can be used as a clock input, which allows multiple independent clock domains.
As an example, a FlexEOS core comprising 3,072 MFCs represents the equivalent of approximately 30,000 ASIC gates. Such a core has a size of 4.5 mm2 in 0.13µm technology, and a configuration file of 28KBytes which can be loaded in 500µs at 100MHz. The maximum measured speed of this core is 700MHz. The FlexEOS software flow is fully automatic, efficient and rapid, and is designed to interface with popular ASIC design flows. Users can quickly and easily map a design to the core, and generate a simulation and timing model for full system verification.
The FlexEOS business model is based on a license fee and royalties related to the production volume and type of macro. About M2000
Three Electronic Design Automation veterans with more than 15 years of custom programmable logic experience, created M2000 S.A. in 1996. The three founders hold numerous patents in the field of configurable logic, and its applications for electronic system verification. M2000’s current vision is to design and develop state of the art configurable logic technology for the rapidly growing reprogrammable System-on-Chip market. Corporate headquarters are located at: Parc Burospace, Bâtiment 1bis, 1 Route de Gisy, Bièvres (91570) France - World Wide Web site: www.m2000.fr